Multi-chip device, method of manufacturing a multi-chip device, and method of forming a metal interconnect
US-11488921-B2 · Nov 1, 2022 · US
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Pelzer Rainer patents
Pelzer Rainer is listed as an inventor on 19 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Pelzer Rainer |
| Total patents | 19 |
| First publication | Feb 23, 2017 |
| Latest publication | Nov 1, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Semiconductor device power metallization layer with stress-relieving heat sink structure
US-11276624-B2 · Mar 15, 2022 · US
Terminal structure of a power semiconductor device
US-11239188-B2 · Feb 1, 2022 · US
Barrier for power metallization in semiconductor devices
US-11127693-B2 · Sep 21, 2021 · US
Semiconductor Device Power Metallization Layer with Stress-Relieving Heat Sink Structure
US-2021183732-A1 · Jun 17, 2021 · US
Semiconductor device having a die pad with a dam-like configuration
US-11031321-B2 · Jun 8, 2021 · US
Method of manufacturing a semiconductor device having a power metallization structure
US-10978395-B2 · Apr 13, 2021 · US
Multi-Chip Device, Method of Manufacturing a Multi-Chip Device, and Method of Forming a Metal Interconnect
US-2021098410-A1 · Apr 1, 2021 · US
Method of Manufacturing a Semiconductor Device Having a Power Metallization Structure
US-2020335448-A1 · Oct 22, 2020 · US
Semiconductor Device Having a Die Pad with a Dam-Like Configuration
US-2020294894-A1 · Sep 17, 2020 · US
Recent patents
Latest publications not already listed above.
Power metallization structure for semiconductor devices
US-10734320-B2 · Aug 4, 2020 · US
Semiconductor device with compressive interlayer
US-10700019-B2 · Jun 30, 2020 · US
Barrier for Power Metallization in Semiconductor Devices
US-2020111754-A1 · Apr 9, 2020 · US
Power Metallization Structure for Semiconductor Devices
US-2020035610-A1 · Jan 30, 2020 · US
Semiconductor Device with Compressive Interlayer
US-2019273050-A1 · Sep 5, 2019 · US
Compressive interlayer having a defined crack-stop edge extension
US-10304782-B2 · May 28, 2019 · US
Compressive Interlayer Having a Defined Crack-Stop Edge Extension
US-2019067209-A1 · Feb 28, 2019 · US
Terminal Structure of a Power Semiconductor Device
US-2018145045-A1 · May 24, 2018 · US
Method, a semiconductor device and a layer arrangement
US-2017053879-A1 · Feb 23, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Infineon Technologies Ag | 13 |
| Infineon Technologies Austria Ag | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/425 | 6 |
| H01L23/53238 | 6 |
| H10W72/01255 | 6 |
| H10W72/01253 | 6 |
| H10W72/01223 | 6 |