Semiconductor device power metallization layer with stress-relieving heat sink structure

Patent metadata

Field	Value
Publication number	US-11276624-B2
Application number	US-201916716789-A
Country	US
Kind code	B2
Filing date	Dec 17, 2019
Priority date	Dec 17, 2019
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a power device formed in the semiconductor substrate;
a metal bilayer formed over the semiconductor substrate, the metal bilayer comprising a discontinuous metal layer formed on and in contact with a continuous base metal layer; and
one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer,
wherein the discontinuous metal layer comprises a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device,
wherein the continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks,
wherein the metal bilayer is an uppermost metallization layer of the semiconductor device or a metallization layer below the uppermost metallization layer.

2. The semiconductor device of claim 1 , wherein a thickness of the discontinuous metal layer is greater than a thickness of the continuous base metal layer or the thickness of the discontinuous metal layer is at least 10 times the thickness of the continuous base metal layer, and wherein the plurality of metal blocks each have a width greater than the thickness of the discontinuous metal layer.

3. The semiconductor device of claim 1 , wherein the plurality of metal blocks is arranged in a honeycomb pattern.

4. The semiconductor device of claim 1 , wherein the discontinuous metal layer comprises copper and has a thickness greater than 10 μm, wherein the continuous base metal layer comprises copper and has a thickness less than 10 μm, and wherein the plurality of metal blocks each have a width greater than the thickness of the discontinuous metal layer.

5. The semiconductor device of claim 1 , wherein a gap between adjacent metal blocks of the plurality of metal blocks is less than both a width of the plurality of metal blocks and a thickness of the discontinuous metal layer.

6. The semiconductor device of claim 5 , wherein the gap between the adjacent metal blocks is less than one third (⅓) the width of the plurality of metal blocks and less than one half (½) the thickness of the discontinuous metal layer.

7. The semiconductor device of claim 5 , wherein the gap between the adjacent metal blocks is less than one quarter (¼) the width of the plurality of metal blocks.

8. The semiconductor device of claim 1 , wherein a ratio of a thickness of the discontinuous metal layer to a thickness of the continuous base metal layer is in a range of 1:2 to 50:1.

9. The semiconductor device of claim 1 , wherein the metal bilayer is the uppermost metallization layer, wherein the one or more contact pads are formed in the metal bilayer, and wherein a gap between adjacent metal blocks of the plurality of metal blocks is filled with molding compound, imide, spin on glass, or paraffin.

10. A semiconductor device, comprising:
a semiconductor substrate; and
a metal bilayer separated from the semiconductor substrate by at least one interlayer dielectric, the metal bilayer comprising a discontinuous metal layer on a continuous base metal layer,
wherein the continuous base metal layer has a thickness which is at most 20% of an overall thickness of the metal bilayer,
wherein the discontinuous metal layer has a thickness which is at least 50% of the overall thickness of the metal bilayer,
wherein the discontinuous metal layer comprises a plurality of metal blocks which are laterally spaced apart from one another and in physical contact with the continuous base metal layer,
wherein the plurality of metal blocks each have a width greater than the thickness of the discontinuous metal layer,
wherein a gap between adjacent metal blocks of the plurality of metal blocks is less than both the width of the plurality of metal blocks and the thickness of the discontinuous metal layer.

11. The semiconductor device of claim 10 , wherein the plurality of metal blocks is arranged in a honeycomb pattern.

12. The semiconductor device of claim 10 , wherein the gap between the adjacent metal blocks is less than one third (⅓) the width of the plurality of metal blocks and less than one half (½) the thickness of the discontinuous metal layer, or wherein the gap between the adjacent metal blocks is less than one quarter (¼) the width of the plurality of metal blocks.

13. The semiconductor device of claim 10 , wherein the metal bilayer is an uppermost metallization layer of the semiconductor device, and wherein the gap between the adjacent metal blocks is filled with molding compound, imide, spin on glass, or paraffin.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Nelhiebel Michael
• Assmann Heiko
• Heitzsch Olaf
• Kriz Jakob
• Lanzerstorfer Sven
• Pelzer Rainer
• Robl Werner
• Weidgans Bernhard
• Zechner Johannes

Classifications

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W40/735

  by melting or evaporation of solids · CPC title