Power Metallization Structure for Semiconductor Devices

Patent metadata

Field	Value
Publication number	US-2020035610-A1
Application number	US-201816048667-A
Country	US
Kind code	A1
Filing date	Jul 30, 2018
Priority date	Jul 30, 2018
Publication date	Jan 30, 2020
Grant date	—

Abstract

A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate; a power metallization structure formed above the semiconductor substrate; a barrier layer formed between the power metallization structure and the semiconductor substrate, the barrier layer configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate, the power metallization structure being in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region; and a passivation layer interposed between the barrier layer and the power metallization structure in a second region.

2 . The semiconductor device of claim 1 , wherein the barrier layer is structured in the second region as a signal routing structure.

3 . The semiconductor device of claim 2 , wherein the power metallization structure is disposed over the signal routing structure in the second region, and wherein the signal routing structure is insulated from the power metallization structure by the passivation layer in the second region.

4 . The semiconductor device of claim 3 , wherein the power metallization structure is structured independently of the signal routing structure in the second region.

5 . The semiconductor device of claim 1 , wherein the first region and the second region are directly adjoining, wherein the power metallization structure and the barrier layer are unpatterned in the first region and the second region, and wherein the passivation layer covers a periphery of the barrier layer in the second region.

6 . The semiconductor device of claim 5 , wherein the barrier layer laterally extends beyond side faces of the power metallization structure in the second region.

7 . The semiconductor device of claim 6 , wherein the barrier layer laterally extends beyond the side faces of the power metallization structure in the second region by between 500 nm and 5 microns.

8 . The semiconductor device of claim 5 , wherein the passivation layer is interposed between the barrier layer and the power metallization structure in a section of the second region spaced apart from the first region.

9 . The semiconductor device of claim 8 , wherein the barrier layer is structured as a signal routing structure in the section of the second region spaced apart from the first region.

10 . The semiconductor device of claim 9 , wherein the power metallization structure is disposed over the signal routing structure in the section of the second region spaced apart from the first region, and wherein the signal routing structure is insulated from the power metallization structure by the passivation layer.

11 . The semiconductor device of claim 10 , wherein the power metallization structure is structured independently of the signal routing structure in the section of the second region spaced apart from the first region.

12 . The semiconductor device of claim 1 , further comprising an intermediate layer interposed between the barrier layer and the passivation layer in the second region, wherein the intermediate layer is structured identically as the barrier layer in the second region.

13 . The semiconductor device of claim 12 , wherein the barrier layer comprises TiW, the intermediate layer comprises AlCu and the power metallization structure comprises Cu.

14 . The semiconductor device of claim 1 , further comprising an intermediate layer interposed between the passivation layer and the power metallization structure in the second region.

15 . The semiconductor device of claim 14 , wherein the barrier layer comprises TiW, the intermediate layer comprises TiW and the power metallization structure comprises Cu.

16 . The semiconductor device of claim 1 , wherein the power metallization structure is omitted above the barrier layer in the second region.

17 . A method of manufacturing a semiconductor device, the method comprising:
forming a barrier layer above a semiconductor substrate, the barrier layer configured to prevent diffusion of metal atoms from above the barrier layer in a direction toward the semiconductor substrate; structuring the barrier layer; and after structuring the barrier layer, forming a power metallization structure above the structured barrier layer without forming an additional barrier layer for the power metallization structure, the power metallization structure being in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region.

18 . The method of claim 17 , wherein forming the power metallization structure comprises:
after structuring the barrier layer, forming an adhesion promoting layer on the barrier layer and a Cu layer on the adhesion promoting layer, the adhesion promoting layer configured to increase adhesion of the power metallization structure to the barrier layer in the first region; forming a mask on the Cu layer, the mask having openings aligned with features previously structured into the barrier layer; and isotropically etching the Cu layer and the adhesion promoting layer through the openings in the mask, to structure the power metallization structure and so that the barrier layer laterally extends beyond side faces of the power metallization structure in regions aligned with the openings in the mask.

19 . The method of claim 17 , further comprising:
before structuring the barrier layer, forming a protective layer on the barrier layer which is configured to prevent oxidation of the barrier layer during the structuring.

20 . The method of claim 19 , wherein forming the power metallization structure comprises:
after structuring the protective layer and the barrier layer, forming a Cu seed layer on the protective layer; forming a mask on the Cu seed layer in a second region; forming a Cu layer on the Cu seed layer in the first region but not in the second region where the mask is present; and after forming the Cu layer, removing the mask and the Cu seed layer from the protective layer in the second region.

21 . The method of claim 19 , wherein forming the power metallization structure comprises:
after structuring the protective layer and the barrier layer, forming a passivation layer on the protective layer; removing the passivation layer in the first region but not in a second region; forming a Cu seed layer on the protective layer in the first region and on the passivation layer in the second region; and forming a Cu layer on the Cu seed layer at least in the first region.

22 . The method of claim 21 , further comprising:
before forming the Cu layer, forming a mask on the Cu seed layer in the second region so that the Cu layer is formed on the Cu seed layer in the first region but not in the second region where the mask is present; and after forming the Cu layer, removing the mask.

23 . The method of claim 21 , wherein the barrier layer is structured in the second region as a signal routing structure, the method further comprising:
structuring the Cu layer in the second region independently of the signal routing structure.

24 . The method of claim 19 , wherein forming the power metallization structure comprises:
after structuring the protective layer and the barrier layer, forming a passivation layer on the protective layer; removing the passivation layer in the first region but not in a second region; and formi

Assignees

• Infineon Technologies Austria Ag

Inventors

• Joshi Ravi Keshav
• Pelzer Rainer
• Buerke Axel
• Schmidbauer Sven
• Nelhiebel Michael

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title