Terminal structure of a power semiconductor device

Patent metadata

Field	Value
Publication number	US-11239188-B2
Application number	US-201715817810-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Nov 21, 2016
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

First claim

What is claimed is:

1. A method of processing a power semiconductor device, the method comprising:
providing a semiconductor body configured to conduct a load current;
forming a first load terminal electrically connected with the semiconductor body and configured to couple the load current into and/or out of the semiconductor body, wherein the first load terminal comprises a metallization having a frontside and a backside, the backside interfacing with a surface of the semiconductor body and the frontside being configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current, wherein forming the first load terminal further comprises:
laterally structuring the frontside of the metallization by forming at least one local elevation of the metallization so that the metallization has a local increase of depth in a region of the at least one local elevation and a lesser, non-zero depth outside the region of the at least one local elevation, the at least one local elevation having a height in an extension direction defined by the distance between a base and a top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top, wherein the at least one local elevation is formed such that the top width amounts to less than 90% of the base width, wherein there is neither a material barrier within the at least one local elevation itself nor between the at least one local elevation and a remaining section of the metallization outside the region of the at least one local elevation.

2. The method of claim 1 , wherein laterally structuring the frontside of the metallization comprises:
forming a conductive layer on top of the surface;
providing a first mask on top of the conductive layer, the first mask including at least one first mask element;
carrying out a first etch processing step to back-thin the conductive layer in sections not covered by the at least one first mask element, wherein the back-thinning of the conductive layer spatially confines the at least one local elevation, and wherein the back-thinning has a first lateral overlap with the at least one first mask element that amounts to at least 1 μm.

3. The method of claim 2 , wherein the top width of the at least one local elevation is smaller than a width of the at least one first mask element by at least 1 μm.

4. The method of claim 2 , wherein the first lateral overlap is formed by means of an etch undercut produced within the first etch processing step.

5. The method of claim 2 , wherein, during the first etch processing step, the lateral extension of the at least one first mask element is reduced from an initial value to an end value, the end value amounting to less than 90% of the initial value.

6. The method of claim 2 , wherein, during the first etch processing step, an etchant is used that is configured to etch each of the conductive layer and the at least one mask element.

7. The method of claim 2 , further comprising, after carrying out the first etch processing step:
providing at least one second mask element in a recess section caused by the first lateral overlap; and
carrying out a second etch processing step to further back-thin the conductive layer in sections not covered by the at least one second mask element, wherein the further back-thinning of the conductive layer spatially confines the at least one local elevation, and wherein the further back-thinning has a second lateral overlap with the at least one second mask element that amounts to at least 1 μm.

8. The method of claim 7 , wherein the second lateral overlap is formed by means of an etch undercut produced within the second etch processing step.

9. The method of claim 1 , wherein laterally structuring the frontside of the metallization comprises:
forming a conductive layer on top of the surface by a first electroplating processing step;
providing a first mask on top of the conductive layer, the first mask including at least one first mask element that spatially confines at least one first opening; and
carrying out a second electroplating processing step to fill the at least one first opening with a conductive material, thereby forming the at least one local elevation.

10. The method of claim 1 , wherein laterally structuring the frontside of the metallization comprises:
forming a conductive layer on top of the surface;
providing a first mask on top of the conductive layer, the first mask including at least one first mask element that spatially confines at least one first opening;
filling the at least one first opening with a conductive material;
providing at least one second mask element on top of the at least one first mask element, the at least one second mask element laterally overlapping with the filled at least one first opening and defining at least one second opening; and
filling the at least one second opening with a conductive material, thereby forming the at least one local elevation.

11. The method of claim 10 , wherein forming the conductive layer, filling the at least one first opening and filling the at least one second opening each comprise carrying out a respective electroplating processing step.

12. The method of claim 1 , wherein laterally structuring the frontside of the metallization comprises:
forming a conductive layer on top of the surface;
providing a first mask on top of the conductive layer, the first mask including at least one first mask element that spatially confines at least one first opening, wherein the at least one first mask element has a width that decreases along the extension direction; and
filling the at least one first opening with a conductive material, thereby forming the at least one local elevation.

13. The method of claim 12 , wherein the difference between the base width and the top width of the at least one local elevation amounts to at least the value of the width decrease of the at least one first mask element.

Assignees

• Infineon Technologies Ag

Inventors

• Zundel Markus
• Pelzer Rainer
• Schneegans Manfred

Classifications

• H10W72/01953

  by etching · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/983

  Reinforcing structures, e.g. collars · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title