Semiconductor device having a die pad with a dam-like configuration

Patent metadata

Field	Value
Publication number	US-11031321-B2
Application number	US-201916354392-A
Country	US
Kind code	B2
Filing date	Mar 15, 2019
Priority date	Mar 15, 2019
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed;
a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and
a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material at a side of the interior region facing away from the semiconductor substrate.

2. The semiconductor device of claim 1 , wherein the interior region of the first metal pad has a thickness in a range of 5 μm to 10 μm, wherein the peripheral region of the first metal pad has a thickness of about 20 μm or greater.

3. The semiconductor device of claim 2 , wherein the semiconductor substrate has a thickness of 60 μm or less.

4. The semiconductor device of claim 1 , wherein the peripheral region of the first metal pad is thicker than the die attach material.

5. The semiconductor device of claim 1 , wherein the die attach material is thicker than the peripheral region of the first metal pad so that a bottom surface of the first interconnect plate or the semiconductor die is disposed above a top surface of the peripheral region of the first metal pad.

6. The semiconductor device of claim 1 , wherein a bottom surface of the first interconnect plate has one or more structures laterally disposed inward from the peripheral region of the first metal pad and vertically extending toward the interior region of the first metal pad.

7. The semiconductor device of claim 1 , wherein the peripheral region of the first metal pad is divided into a plurality of segments, and wherein neighboring ones of the segments are laterally separated by a gap.

8. The semiconductor device of claim 1 , wherein the power transistor comprises a plurality of output channels, each output channel configured to deliver current to a load, wherein the power transistor comprises an individual active area for each output channel, and wherein the first metal pad covers substantially a first one of the active areas of the power transistor.

9. The semiconductor device of claim 8 , further comprising:
a plurality of additional metal pads formed above the semiconductor substrate, each additional metal pad covering substantially a corresponding one of the active areas of the power transistor, each additional metal pad being electrically connected to a source or emitter region in the active area substantially covered by the metal pad, each metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and
a plurality of additional interconnect plates, each additional interconnect plate being attached to the interior region of a corresponding one of the additional metal pads by a die attach material at a side of the interior region facing away from the semiconductor substrate.

10. The semiconductor device of claim 1 , further comprising one or more logic devices integrated in a different region of the semiconductor substrate as the power transistor.

11. The semiconductor device of claim 1 , wherein the first metal pad is a Cu pad, and wherein the first interconnect plate is a Cu clip.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a power transistor in a semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed;
forming a first metal pad above the semiconductor substrate and which covers substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and
attaching a first interconnect plate or a semiconductor die to the interior region of the first metal pad by a die attach material at a side of the interior region facing away from the semiconductor substrate.

13. The method of claim 12 , wherein forming the first metal pad comprises:
depositing a first Cu layer above the semiconductor substrate and which covers substantially all of the active area of the power transistor;
forming a mask on a part of the first Cu layer which corresponds to the interior region of the first metal pad, the mask configured to prevent Cu deposition; and
depositing a second Cu layer on a part of the first Cu layer unprotected by the mask to form the peripheral region of the first metal pad, the interior region of the first metal pad being formed by the part of the first Cu layer protected by the mask during the depositing of the second Cu layer.

14. The method of claim 13 , wherein the first Cu layer has a thickness in a range of 5 μm to 10 μm, and wherein the second Cu layer has a thickness in a range of 10 μm to 20 μm.

15. The method of claim 12 , wherein forming the first metal pad comprises:
depositing a Cu layer above the semiconductor substrate and which covers substantially all of the active area of the power transistor;
forming a mask on a part of the Cu layer which corresponds to the peripheral region of the first metal pad, the mask configured to prevent Cu etching; and
etching a part of the Cu layer unprotected by the mask to form the interior region of the first metal pad, the peripheral region of the first metal pad being formed by the part of the Cu layer protected by the mask during the etching of the Cu layer.

16. The method of claim 15 , wherein the thickness of the Cu layer as deposited is about 20 μm or more, and wherein the thickness of the etched part of the Cu layer is in a range of 5 μm to 10 μm.

17. The method of claim 12 , wherein the peripheral region of the first metal pad is thicker than the die attach material, and wherein attaching the first interconnect plate or the semiconductor die to the interior region of the first metal pad comprises:
depositing the die attach material on the interior region of the first metal pad; and
placing the first interconnect plate in contact with the die attach material while using the peripheral region of the first metal pad to align the first interconnect plate with the first metal pad.

18. The method of claim 12 , wherein the die attach material is thicker than the peripheral region of the first metal pad, and wherein attaching the first interconnect plate or the semiconductor die to the interior region of the first metal pad comprises:
depositing the die attach material on the interior region of the first metal pad; and
placing the first interconnect plate in contact with the die attach material while using surface tension of the die attach material to align the first interconnect plate with the first metal pad.

19. The method of claim 12 , wherein a bottom surface of the first interconnect plate has one or more structures laterally disposed inward from the peripheral region of the first metal pad, and wherein attaching the first interconnect plate or the semiconductor die to the interior region of

Assignees

• Infineon Technologies Ag

Inventors

• Pelzer Rainer
• Lopez Fortunato
• Maglangit Antonia
• Shikh Zakaria Siti Amira Faisha

Classifications

• H10W72/07653

  changes in shapes · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/04

  of leadframes · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/045

  for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD] · CPC title