Barrier for power metallization in semiconductor devices

Patent metadata

Field	Value
Publication number	US-11127693-B2
Application number	US-201916710044-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Aug 25, 2017
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a structured interlayer on a substrate;
a structured power metallization on the structured interlayer; and
a barrier on the structured power metallization and configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization,
wherein a first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns,
wherein the structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer,
wherein the first defined edge of the structured power metallization has a sidewall which slopes inward.

2. The semiconductor device of claim 1 , wherein the sidewall of the first defined edge of the structured power metallization slopes inward at an angle greater than 0 degrees and up to 10 degrees relative to a normal line which is perpendicular to a surface of the structured interlayer on which the structured power metallization is disposed.

3. The semiconductor device of claim 1 , wherein the barrier comprises one or more of SiN, SiO, SiC, SiCN, AlO, and AlN.

4. The semiconductor device of claim 1 , wherein the barrier is a single layer comprising one of SiN, SiO, SiC, SiCN, AlO, or AlN.

5. The semiconductor device of claim 1 , wherein the barrier comprises a stack of layers.

6. The semiconductor device of claim 1 , wherein the barrier comprises a first SiN layer arranged closest to the structured power metallization, a SiO layer on the first SiN layer, and a second SiN layer on the SiO layer, and wherein the second SiN layer is thicker than the first SiN layer.

7. The semiconductor device of claim 6 , wherein the SiO layer is thicker than the first SiN layer and thinner than the second SiN layer.

8. The semiconductor device of claim 6 , wherein the SiO layer is at least two times as thick as the first SiN layer, and wherein the second SiN layer is at least three times as thick as the first SiN layer.

9. The semiconductor device of claim 1 , wherein the barrier has a generally uniform thickness and conforms to a surface topography of the structured power metallization.

10. The semiconductor device of claim 1 , wherein the sidewall of the first defined edge of the structured power metallization has an outward projecting ledge adjacent to the structured interlayer, and wherein the outward projecting ledge has a lateral dimension which is less than half the thickness of the barrier.

11. The semiconductor device of claim 1 , further comprising:
an imide on the barrier; and
a molding compound on the imide.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a structured interlayer on a substrate;
forming a structured power metallization on the structured interlayer, wherein a first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns, wherein the structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer;
etching the first defined edge of the structured power metallization so that the first defined edge of the structured power metallization has a sidewall which slopes inward; and
forming a barrier on the structured power metallization, the barrier configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization.

13. The method of claim 12 , wherein etching the first defined edge of the structured power metallization comprises:
wet chemical etching the first defined edge of the structured power metallization for a duration greater than 20 seconds and so that the sidewall slopes inward at an angle greater than 0 degrees and up to 10 degrees relative to a normal line which is perpendicular to a surface of the structured interlayer on which the structured power metallization is disposed.

14. The method of claim 13 , wherein the first defined edge of the structured power metallization is wet chemical etched for up to 90 seconds.

15. The method of claim 12 , wherein forming the barrier on the structured power metallization comprises:
depositing one or more of SiN, SiO, SiC, SiCN, AlO, and AlN on the structured power metallization.

16. The method of claim 12 , wherein forming the barrier on the structured power metallization comprises:
forming a first SiN layer arranged closest to the structured power metallization;
forming a SiO layer on the first SiN layer; and
forming a second SiN layer on the SiO layer,
wherein the second SiN layer is thicker than the first SiN layer.

17. The method of claim 16 , wherein the SiO layer is thicker than the first SiN layer and thinner than the second SiN layer.

18. The method of claim 16 , wherein the SiO layer is at least two times as thick as the first SiN layer, and wherein the second SiN layer is at least three times as thick as the first SiN layer.

19. The method of claim 12 , wherein the barrier has a generally uniform thickness and conforms to a surface topography of the structured power metallization.

20. The method of claim 12 , further comprising:
forming an imide on the barrier; and
molding the semiconductor device with a molding compound which covers the imide.

Assignees

• Infineon Technologies Ag

Inventors

• Gatterbauer Johann
• Albers Katrin
• Busch Joerg
• Goller Klaus
• Mais Norbert
• Kolitsch Marianne
• Nelhiebel Michael
• Pelzer Rainer
• Weidgans Bernhard

Classifications

• H10W72/01255

  by using masks · CPC title

• H10W72/01253

  by etching · CPC title

• H10W72/01223

  in liquid form, e.g. by dispensing droplets or by screen printing · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/234

  Cross-sectional shape, i.e. in side view · CPC title