Power metallization structure for semiconductor devices

Patent metadata

Field	Value
Publication number	US-10734320-B2
Application number	US-201816048667-A
Country	US
Kind code	B2
Filing date	Jul 30, 2018
Priority date	Jul 30, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a power metallization structure formed above the semiconductor substrate;
a barrier layer formed between the power metallization structure and the semiconductor substrate, the barrier layer configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate, the power metallization structure being in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region; and
a passivation layer interposed between the barrier layer and the power metallization structure in a second region,
wherein the barrier layer is structured as a signal routing structure in the second region,
wherein the power metallization structure is disposed over the signal routing structure in the second region,
wherein the signal routing structure is insulated from the power metallization structure by the passivation layer in the second region.

2. The semiconductor device of claim 1 , wherein the power metallization structure is structured independently of the signal routing structure in the second region.

3. The semiconductor device of claim 1 , wherein the first region and the second region are directly adjoining, wherein the power metallization structure and the barrier layer are unpatterned in the first region, and wherein the passivation layer covers a periphery of the barrier layer in the second region.

4. The semiconductor device of claim 3 , wherein the barrier layer laterally extends beyond side faces of the power metallization structure in the second region.

5. The semiconductor device of claim 4 , wherein the barrier layer laterally extends beyond the side faces of the power metallization structure in the second region by between 500 nm and 5 microns.

6. The semiconductor device of claim 1 , further comprising an intermediate layer interposed between the barrier layer and the passivation layer in the second region, wherein the intermediate layer is structured identically as the barrier layer in the second region.

7. The semiconductor device of claim 6 , wherein the barrier layer comprises TiW, the intermediate layer comprises AlCu and the power metallization structure comprises Cu.

8. The semiconductor device of claim 1 , further comprising an intermediate layer interposed between the passivation layer and the power metallization structure in the second region.

9. The semiconductor device of claim 8 , wherein the barrier layer comprises TiW, the intermediate layer comprises TiW and the power metallization structure comprises Cu.

10. The semiconductor device of claim 1 , wherein the power metallization structure is omitted above the barrier layer in the second region.

11. A semiconductor device, comprising:
a semiconductor substrate;
a power metallization structure formed above the semiconductor substrate;
a barrier layer formed between the power metallization structure and the semiconductor substrate, the barrier layer configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate, the power metallization structure being in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region; and
a passivation layer interposed between the barrier layer and the power metallization structure in a second section of a second region,
wherein the barrier layer is structured as a signal routing structure in a first section of the second region,
wherein the first section of the second region is spaced apart from the first region by the second section of the second region,
wherein no metallization structure is present above the signal routing structure.

12. The semiconductor device of claim 11 , wherein the first region and the second region are directly adjoining, wherein the power metallization structure and the barrier layer are unpatterned in the first region, and wherein the passivation layer covers a periphery of the barrier layer in the second section of the second region.

13. The semiconductor device of claim 12 , wherein the barrier layer laterally extends beyond side faces of the power metallization structure in the second section of the second region.

14. The semiconductor device of claim 13 , wherein the barrier layer laterally extends beyond the side faces of the power metallization structure in the second section of the second region by between 500 nm and 5 microns.

15. The semiconductor device of claim 11 , further comprising an intermediate layer interposed between the barrier layer and the passivation layer in the first section of the second region, wherein the intermediate layer is structured identically as the barrier layer in the second section of the second region.

16. The semiconductor device of claim 15 , wherein the barrier layer comprises TiW, the intermediate layer comprises AlCu and the power metallization structure comprises Cu.

17. The semiconductor device of claim 11 , further comprising an intermediate layer interposed between the passivation layer and the power metallization structure in the second section of the second region.

18. The semiconductor device of claim 17 , wherein the barrier layer comprises TiW, the intermediate layer comprises TiW and the power metallization structure comprises Cu.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Joshi Ravi Keshav
• Pelzer Rainer
• Buerke Axel
• Schmidbauer Sven
• Nelhiebel Michael

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title