Semiconductor device with compressive interlayer

Patent metadata

Field	Value
Publication number	US-10700019-B2
Application number	US-201916418006-A
Country	US
Kind code	B2
Filing date	May 21, 2019
Priority date	Aug 25, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a structured interlayer on the substrate and having a defined edge; and
a structured metallization on the structured interlayer and having a defined edge which is immediately adjacent to the defined edge of the structured interlayer and faces the same direction from a plan view perspective of the semiconductor device as the defined edge of the structured interlayer,
wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer,
wherein the structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

2. The semiconductor device of claim 1 , wherein the substrate is an interlevel dielectric.

3. The semiconductor device of claim 1 , wherein the substrate is a semiconductor substrate.

4. The semiconductor device of claim 3 , wherein the semiconductor substrate comprises one of Si, GaN on Si, GaN on SiC, GaN on sapphire, and SiC.

5. The semiconductor device of claim 1 , wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 1 micron.

6. The semiconductor device of claim 1 , wherein the structured interlayer and the structured metallization are applied over a front side of the substrate, and wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by more than 0.5 microns and less than 30 microns.

7. The semiconductor device of claim 1 , wherein the substrate has a non-planar surface on which the structured interlayer is formed, and wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 2 microns and less than 30 microns.

8. The semiconductor device of claim 7 , wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 4 microns and less than 15 microns.

9. The semiconductor device of claim 1 , wherein the substrate has a non-planar surface on which the structured interlayer is formed, wherein the defined edge of the structured metallization terminates between raised features of the non-planar surface, and wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 3 microns.

10. The semiconductor device of claim 9 , wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 4 microns.

11. The semiconductor device of claim 1 , wherein the substrate has a non-planar surface on which the structured interlayer is formed, wherein the defined edge of the structured metallization terminates over raised features of the non-planar surface, and wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 3 microns.

12. The semiconductor device of claim 11 , wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 4 microns.

13. The semiconductor device of claim 1 , wherein the substrate has a non-planar surface on which the structured interlayer is formed, wherein the defined edge of the structured metallization terminates over a raised feature of the non-planar surface, and wherein the defined edge of the structured interlayer extends beyond the raised feature of the non-planar surface.

14. The semiconductor device of claim 1 , wherein the substrate has a planar surface on which the structured interlayer is formed, and wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns and less than 10 microns.

15. The semiconductor device of claim 1 , wherein the structured metallization comprises multiple layers of metal.

16. The semiconductor device of claim 1 , wherein the structured metallization is disposed directly on the structured interlayer.

17. The semiconductor device of claim 1 , wherein the structured metallization comprises Cu, and wherein the structured interlayer comprises at least one of TiW and W.

18. The semiconductor device of claim 1 , wherein the structured metallization comprises Al, and wherein the structured interlayer comprises at least one of TiN and W.

19. The semiconductor device of claim 1 , wherein the structured metallization comprises Au.

20. The semiconductor device of claim 1 , wherein the structured interlayer comprises a plurality of layers, wherein at least one of the layers has a compressive residual stress at room temperature, wherein at least one of the layers has a tensile residual stress at room temperature, and wherein the structured interlayer has an overall compressive residual stress at room temperature.

21. The semiconductor device of claim 1 , wherein the structured interlayer and the structured metallization are applied over a back side of the substrate, and wherein the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by between 2 microns and 100 microns, or up to 10% of a lateral dimension of the structured metallization in a direction perpendicular to the defined edges of the structured metallization.

22. A method of manufacturing a semiconductor device, the method comprising:
forming a structured interlayer on a substrate, the structured interlayer having a defined edge; and
forming a structured metallization on the structured interlayer, the structured metallization having a defined edge which is immediately adjacent to the defined edge of the structured interlayer and faces the same direction from a plan view perspective of the semiconductor device as the defined edge of the structured interlayer,
wherein the structured interlayer is formed so that the defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns and the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer,
wherein the structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

23. The method of claim 22 , wherein forming the structured interlayer and forming the structured metallization comprises:
depositing an interlayer material system on the substrate, the interlayer material system having an overall compressive residual stress at room temperature;
depositing and patterning metal on the interlayer material system;
using the deposited and structured metal as a mask to remove the part of the interlayer material system unprotected by the deposited and structured metal; and
laterally etching the deposited and structured metal selective to the interlayer material system so that the defined edge of the interlayer material system extends beyond the defined edge of the depos

Assignees

• Infineon Technologies Ag

Inventors

• Mataln Marianne
• Nelhiebel Michael
• Pelzer Rainer
• Weidgans Bernhard

Classifications

• H10W72/01255

  by using masks · CPC title

• H10W72/01253

  by etching · CPC title

• H10W72/01223

  in liquid form, e.g. by dispensing droplets or by screen printing · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/234

  Cross-sectional shape, i.e. in side view · CPC title