Memory interface
US-12591429-B2 · Mar 31, 2026 · US
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Noguchi Hiroki patents
Noguchi Hiroki is listed as an inventor on 141 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Noguchi Hiroki |
| Total patents | 141 |
| First publication | Oct 1, 2019 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Circuit with swept voltage on bit line or bit line bar
US-12562216-B2 · Feb 24, 2026 · US
Dynamic error monitor and repair
US-2026031173-A1 · Jan 29, 2026 · US
One-time-programmable memory
US-12518841-B2 · Jan 6, 2026 · US
Memory interface
US-12517679-B2 · Jan 6, 2026 · US
Second word line combined with y-mux signal in high voltage memory program
US-2025364034-A1 · Nov 27, 2025 · US
Dynamic error monitor and repair
US-12482531-B2 · Nov 25, 2025 · US
Memory interface
US-2025328290-A1 · Oct 23, 2025 · US
Method and system for replacement of memory cells
US-2025329405-A1 · Oct 23, 2025 · US
Memory error detection and correction
US-2025321826-A1 · Oct 16, 2025 · US
Recent patents
Latest publications not already listed above.
Non-volatile static random access memory (nvsram) with multiple magnetic tunnel junction cells
US-2025322873-A1 · Oct 16, 2025 · US
Magnetic device and magnetic random access memory
US-2025318438-A1 · Oct 9, 2025 · US
Second word line combined with y-mux signal in high voltage memory program
US-12412620-B2 · Sep 9, 2025 · US
Vertical interconnect structures in three-dimensional integrated circuits
US-2025279398-A1 · Sep 4, 2025 · US
Semiconductor device and method for forming the same
US-2025267877-A1 · Aug 21, 2025 · US
Non-volatile static random access memory (NVSRAM) with multiple magnetic tunnel junction cells
US-12380950-B2 · Aug 5, 2025 · US
Method and system for replacement of memory cells
US-12374419-B2 · Jul 29, 2025 · US
Magnetic device and magnetic random access memory
US-12356868-B2 · Jul 8, 2025 · US
Nonvolatile sram
US-2025210107-A1 · Jun 26, 2025 · US
Method and system for refresh of memory devices
US-12322432-B2 · Jun 3, 2025 · US
Semiconductor device and method for forming the same
US-12317513-B2 · May 27, 2025 · US
Sensing amplifier, method and controller for sensing memory cell
US-12288577-B2 · Apr 29, 2025 · US
Memory device with write pulse trimming
US-2025118367-A1 · Apr 10, 2025 · US
Vertical interconnect structures in three-dimensional integrated circuits
US-12261152-B2 · Mar 25, 2025 · US
Nonvolatile SRAM
US-12254923-B2 · Mar 18, 2025 · US
Bit line direct charge
US-2025078907-A1 · Mar 6, 2025 · US
Memory error detection and correction
US-12229003-B2 · Feb 18, 2025 · US
Semiconductor MRAM device and method
US-12225734-B2 · Feb 11, 2025 · US
Memory device with write pulse trimming
US-12165704-B2 · Dec 10, 2024 · US
Structure for multiple sense amplifiers of memory device
US-2024395290-A1 · Nov 28, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 144 |
| Aist | 1 |
| Taiwan Semiconductor Mfg Co Ltd | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/1673 | 38 |
| G11C11/1675 | 37 |
| G11C11/1655 | 34 |
| G11C11/161 | 30 |
| G11C29/42 | 28 |