Method and system for replacement of memory cells

Patent metadata

Field	Value
Publication number	US-12374419-B2
Application number	US-202418749098-A
Country	US
Kind code	B2
Filing date	Jun 20, 2024
Priority date	Feb 26, 2020
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A memory system is provided. The memory system includes an error correction code circuit configured to correct a maximum of N error bits in each of multiple read data and a monitor circuit configured to monitor multiple fail word addresses associated with M error bits, and further configured to output a first word address in the fail word addresses to replace first memory locations corresponding to the first word address. Each of the fail word addresses corresponds to one of multiple counter values, and the first word address corresponds to a maximum value of the counter values.

First claim

What is claimed is:

1. A memory system, comprising:
a monitor circuit configured to adjust a plurality of values in an error table when a plurality of first fail word addresses associated with a plurality of memory cells in a first memory array are in the error table, and further configured to record a second fail word address into the error table when the second fail word address is different from the plurality of first fail word addresses.

2. The memory system of claim 1 , further comprising:
an error correction code circuit configured to correct a maximum of N error bits in each of a plurality of read data to generate an error determination signal corresponding to the plurality of first fail word addresses and the second fail word address,
wherein the monitor circuit is further configured to monitor the plurality of first fail word addresses associated with M error bits,
wherein M and N are positive integers and different from each other.

3. The memory system of claim 2 , wherein M is smaller than N.

4. The memory system of claim 1 , wherein the monitor circuit comprises:
a compare circuit configured to compare the plurality of first fail word addresses and the second fail word address with a plurality of stored fail word addresses to determine whether the plurality of first fail word addresses and the second fail word address are in the error table.

5. The memory system of claim 1 , further comprising:
an error correction code circuit configured to correct error bits in each of a plurality of read data to generate an error determination signal to the monitor circuit, wherein the error determination signal corresponds to the plurality of first fail word addresses and the second fail word address,
wherein the plurality of values are associated a number of times the error determination signal indicates the plurality of first fail word addresses.

6. The memory system of claim 1 , further comprising:
a compare circuit configured to compare the plurality of first fail word addresses and the second fail word address with a plurality of stored fail word addresses to determine whether the plurality of first fail word addresses and the second fail word address are in the error table; and
a control circuit configured to record the second fail word address and a corresponding value in the error table in response to the plurality of stored fail word addresses excluding the second fail word address.

7. The memory system of claim 6 , wherein the control circuit is further configured to generate an increment signal to increment the plurality of values in response to the plurality of first fail word addresses being identical with corresponding ones in the plurality of stored fail word addresses.

8. The memory system of claim 7 , wherein the control circuit is further configured to compare a maximum value of the plurality of values and the value corresponding to the second fail word address with a threshold value to transmit a replacement word address.

9. The memory system of claim 8 , further comprising:
a replace circuit configured to replace memory locations, corresponding to the replacement word address, with backup memory locations.

10. The memory system of claim 8 , further comprising:
a replace circuit configured to replace memory locations, corresponding to the replacement word address, with backup memory locations in an replacement operation; and
a processing unit configured to determine a period of the replacing operation.

11. A method, comprising:
accessing a plurality of first memory cells corresponding to a first memory address;
comparing the first memory address with a plurality of second memory addresses to generate a comparison signal;
recording, in response to the comparison signal, a first counter value corresponding to the first memory address and keeping a plurality of second counter values corresponding to the plurality of second memory addresses; and
identifying a memory address corresponding to a maximal value in the first counter value and the plurality of second counter values to replace the memory address with a backup memory location.

12. The method of claim 11 , further comprising:
accessing a plurality of second memory cells corresponding to a third memory address;
comparing the third memory address with the plurality of second memory addresses to generate the comparison signal; and
in response to the comparison signal indicating that the third memory address is identical with one of the plurality of second memory addresses, incrementing a corresponding value in the plurality of second counter values by 1.

13. The method of claim 11 , further comprising:
sorting, according to the first counter value and the plurality of second counter values, the first memory address and the plurality of second memory addresses to place a bottom memory address corresponding to a minimal value in the first counter value and the plurality of second counter values in a bottom entry of an error table and to place a top memory address corresponding to the maximal value in the first counter value and the plurality of second counter values in a top entry of the error table; and
outputting the top memory address as the memory address.

14. The method of claim 11 , further comprising:
when the maximal value is greater than a threshold value, outputting the memory address for replacing the memory address with the backup memory location.

15. The method of claim 11 , wherein the plurality of second counter values are greater than the first counter value.

16. The method of claim 11 , further comprising:
removing the first counter value or the one in the second counter values corresponding to the memory address.

17. A method, comprising:
setting, by a processor, a monitor circuit to record a plurality of first fail word addresses associated with M error bits in an error table;
correcting, by an error correction code circuit, N error bits in each of a plurality of read data to generate an error determination signal, wherein M and N are natural numbers and N is greater than M; and
setting, by the processor, the monitor circuit to record a plurality of second fail word addresses associated with N error bits in the error table and a plurality of counter values corresponding to the plurality of second fail word addresses.

18. The method of claim 17 , further comprising:
comparing a received fail word address with the plurality of second fail word addresses in the error table to increment a corresponding counter value, associated with the received fail word address, in the plurality of counter values;
updating a fail word address that is stored in a top entry of the error table by a third fail word address; and
replacing memory locations based on the updated fail word address stored in the top entry of the error table.

19. The method of claim 18 , wherein replacing the memory locations comprises:
replacing the memory locations periodically with a plurality of backup memory locations.

20. The method of claim 18 , further comprising:
removing the updated fail word address in the top entry of the error table after replacing the memory locations; and
moving up a fourth fail word address originally stored in a entry below the top entry of the error table.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Noguchi Hiroki

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/72

  with optimized replacement algorithms · CPC title

• G11C29/20

  using counters or linear-feedback shift registers [LFSR] · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C29/4401

  for self repair · CPC title