Second word line combined with y-mux signal in high voltage memory program

Patent metadata

Field	Value
Publication number	US-12412620-B2
Application number	US-202318361559-A
Country	US
Kind code	B2
Filing date	Jul 28, 2023
Priority date	May 26, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of memory cells arranged over a plurality of rows and a plurality of columns;
wherein each of the memory cells comprises:
a first metal-oxide-semiconductor (MOS) transistor coupled to a corresponding one of a plurality of first word lines, wherein the plurality of first word lines are arranged along the plurality of rows;
a second MOS transistor coupled to the first MOS transistor and a corresponding one of a plurality of second word lines, wherein the plurality of second word lines are arranged along the plurality of columns;
a memory element; and
a third MOS transistor;
wherein the third MOS transistor, the memory element, the second MOS transistor, and the first MOS transistor are connected in series, and wherein the first MOS transistor and the second MOS transistor are one of n-type MOS (NMOS) transistors or p-type MOS (PMOS) transistors, and the third MOS transistor is another one of NMOS transistor or PMOS transistor different from the first and second MOS transistors.

2. The memory device of claim 1 , wherein each of the first word lines is connected to the respective first MOS transistors of a first subset of the memory cells disposed along a corresponding one of the rows.

3. The memory device of claim 1 , further comprising the plurality of second word lines arranged along the plurality of columns, respectively, wherein each of the second word lines is connected to the respective second MOS transistors of a second subset of the memory cells disposed along a corresponding one of the columns.

4. The memory device of claim 1 , further comprising a plurality of bit lines arranged along the plurality of columns, respectively, wherein each of the bit lines is connected to the respective third MOS transistors of a third subset of the memory cells disposed along a corresponding one of the columns.

5. The memory device of claim 1 , wherein the memory element is a resistor.

6. The memory device of claim 1 , wherein the first MOS transistor and the second MOS transistor are each an NMOS transistor and the third MOS transistor is a PMOS transistor.

7. The memory device of claim 1 , wherein the first MOS transistor and the second MOS transistor are each a PMOS transistor and the third MOS transistor is an NMOS transistor.

8. The memory device of claim 1 , wherein each of the memory cells further comprises a fourth MOS transistor coupled in between the third MOS transistor and the memory element.

9. The memory device of claim 1 , wherein each of the memory cells further comprises a fourth MOS transistor coupled in between the second MOS transistor and the memory element.

10. A memory device, comprising:
a first memory cell that comprises:
a first metal-oxide-semiconductor (MOS) transistor coupled to a first one of a plurality of first word lines, wherein the plurality of first word lines are arranged along a row direction;
a second MOS transistor coupled to the first MOS transistor and a first one of a plurality of second word lines, wherein the plurality of second word lines are arranged along a column direction;
a memory element; and
a third MOS transistor coupled to a first one of a plurality of bit lines;
wherein the first MOS transistor, the second MOS transistor, the memory element, and the third MOS transistor are connected in series, and
wherein the first MOS transistor and the second MOS transistor are one of n-type MOS (NMOS) transistors or p-type MOS (PMOS) transistors, and the third MOS transistor is another one of NMOS transistor or PMOS transistor different from the first and second MOS transistors.

11. The memory device of claim 10 , further comprising:
a second memory cell that comprises:
a fourth MOS transistor coupled to a second one of the plurality of first word lines;
a fifth MOS transistor coupled to the first one of the plurality of second word lines;
a second memory element; and
a sixth MOS transistor coupled to the first one of the plurality of bit lines;
wherein the fourth MOS transistor, the fifth MOS transistor, the second memory element, and the sixth MOS transistor are connected in series.

12. The memory device of claim 11 , further comprising:
a third memory cell that comprises:
a seventh MOS transistor coupled to the first one of the plurality of first word lines;
an eighth MOS transistor coupled to a second one of the plurality of second word lines;
a third memory element; and
a ninth MOS transistor coupled to a second one of the plurality of bit lines;
wherein the seventh MOS transistor, the eighth MOS transistor, the third memory element, and the ninth MOS transistor are connected in series.

13. The memory device of claim 12 , wherein the first word lines extend along a first direction, while the second word lines and the bit lines extend along a second direction.

14. The memory device of claim 10 , wherein the memory element is a resistor.

15. The memory device of claim 10 , wherein the first MOS transistor and the second MOS transistor are each an NMOS transistor and the third MOS transistor is a PMOS transistor.

16. The memory device of claim 10 , wherein the first MOS transistor and the second MOS transistor are each a PMOS transistor and the third MOS transistor is an NMOS transistor.

17. The memory device of claim 10 , wherein the first memory cell further comprises a fourth MOS transistor coupled in between the third MOS transistor and the memory element.

18. The memory device of claim 10 , wherein the first memory cell further comprises a fourth MOS transistor coupled in between the second MOS transistor and the memory element.

19. A memory device, comprising:
a plurality of memory cells arranged over a plurality of rows and a plurality of columns;
wherein each of the memory cells comprises:
a first metal-oxide-semiconductor (MOS) transistor coupled to a corresponding one of a plurality of word lines, wherein the plurality of first word lines are arranged along the plurality of rows;
a second MOS transistor coupled to the first MOS transistor and a corresponding one of a plurality of second word lines, wherein the plurality of second word lines are arranged along the plurality of columns;
a memory element coupled to the second MOS transistor; and
a third MOS transistor coupled to the memory element and a corresponding one of a plurality of bit lines;

wherein the third MOS transistor, the memory element, the second MOS transistor, and the first MOS transistor are connected in series, and
wherein the first MOS transistor and the second MOS transistor are one of n-type MOS (NMOS) transistors or p-type MOS (PMOS) transistors, and the third MOS transistor is another one of NMOS transistor or PMOS transistor different from the first and second MOS transistors.

20. The memory device of claim 19 , wherein the memory element is a resistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yamauchi Yoshitaka
• Chang Meng-Sheng
• Noguchi Hiroki
• Yuh Perng-Fei

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title