Memory error detection and correction

Patent metadata

Field	Value
Publication number	US-12229003-B2
Application number	US-202318230619-A
Country	US
Kind code	B2
Filing date	Aug 4, 2023
Priority date	Sep 28, 2018
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of memory macros, each including an array of memory cells, and a first error correction code (ECC) circuit configured to receive data from the respective memory macro and carry out a subset of steps in an error detection and correction operation by detecting data errors in the received data; and
a second ECC circuit communicatively coupled to each of the plurality of memory macros and configured to receive the detected data errors from each of the first ECC circuits of the plurality of memory macros and carry out remainder steps of the error detection and correction operation, the remainder steps including correcting the data errors and writing the corrected data to the array of memory cells in the memory macro,
the first ECC circuit being further configured to end the error detection and correction operation for the received data when the first ECC circuit detects no error in the received data.

2. The memory device of claim 1 , wherein the memory macros each comprise a magnetic random access memory (MRAM) macro.

3. The memory device of claim 2 , wherein the MRAM macros each further comprise:
an array of MRAM bit cells, each MRAM bit cell comprising:
a magnetic tunnel junction element;
an access transistor coupled to the magnetic tunnel junction element;
a first bit line coupled to the access transistor;
a second bit line coupled to the magnetic tunnel junction element;
a word line coupled to the gate of the access transistor; and
local input-output circuitry coupled to the first and second bit lines of the MRAM bit cells.

4. The memory device of claim 3 , wherein the first ECC circuit comprises:
a first syndrome s1 generator coupled to the first and second bit lines;
a second syndrome s3 generator coupled to the first and second bit lines;
an error check circuit coupled to outputs of each of the first syndrome s1 generator and the second syndrome s3 generator.

5. The memory device of claim 4 , wherein the second ECC circuit comprises:
an encoder (EN) calculation circuit coupled to the local input-output circuitry;
a syndrome s1{circumflex over ( )}3 calculation circuit coupled to the output of the first syndrome s1 generator;
a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator;
a syndrome comparator coupled to the output of the syndrome s1{circumflex over ( )}3 generator and the output of the second syndrome s3 generator;
a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome sl inversion circuit;
an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and
a check bit generator circuit to correct the MRAM cells with an error.

6. The memory device of claim 3 , wherein the first ECC circuit comprises:
a first syndrome s1 generator coupled to the first and second bit lines;
a second syndrome s3 generator coupled to the first and second bit lines;
an EN calculation circuit coupled to the local input-output circuitry;
a syndrome s1{circumflex over ( )}3 calculation circuit coupled to the output of the first syndrome s1 generator;
an error check circuit coupled to the output of each of the first syndrome sl generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1{circumflex over ( )}3 calculation circuit.

7. The memory device of claim 6 , wherein the second ECC circuit comprises:
a syndrome sl inversion circuit coupled to the output of the first syndrome s1 generator;
a syndrome comparator coupled to the output of the syndrome s1{circumflex over ( )}3 generator and the output of the second syndrome s3 generator;
a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit; an error correction circuit coupled to the local input-output circuitry, the syndrome s1 generator, and the GF multi calculation circuit; and
a check bit generator circuit to correct the MRAM cells with an error.

8. The memory device of claim 3 , wherein the first ECC circuit comprises:
a first syndrome s1 generator coupled to the first and second bit lines;
a second syndrome s3 generator coupled to the first and second bit lines;
an EN calculation circuit coupled to the local input-output circuitry;
a syndrome s1{circumflex over ( )}3 calculation circuit coupled to the output of the first syndrome s1 generator;
an error check circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1{circumflex over ( )}3 calculation circuit;
a syndrome s1 inversion circuit coupled to the output of the first syndrome s1 generator;
a syndrome comparator coupled to the output of the syndrome s1{circumflex over ( )}3 generator and the output of the second syndrome s3 generator; and
a GF multi calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 inversion circuit.

9. The memory device of claim 8 , wherein the second ECC circuit comprises:
an error correction circuit coupled to the local input-output circuitry, the syndrome sl generator, and the GF multi calculation circuit; and
a check bit generator circuit to correct the MRAM cells with an error.

10. A method, comprising:
providing a plurality of memory macros, each including an array of memory cells and a first ECC circuit;
providing a second ECC circuit communicatively coupled to each of the plurality of memory macros;
refreshing the memory arrays, including carrying out an error detection and correction operation, including carrying out a subset of steps in an error detection and correction operation by checking for data errors in the memory arrays with the first ECC circuits in the respective memory macros;
if any data error is detected by one of the plurality of the first ECC circuits, carrying out remainder steps of the error detection and correction operation in the second ECC circuit, the remainder steps including:
forwarding the detected data errors from the first ECC circuit to the second ECC circuit;
correcting the data error by the second ECC circuit; and
writing the corrected data to the respective memory array; and

if no data error is detected by one of the plurality of the first ECC circuits, ending the error detection and correction operation for the respective memory macro.

11. The method of claim 10 , wherein checking for data errors in each of the memory arrays with the first ECC circuits comprises:
generating a syndrome s1 based on data received from the MEMORY array;
generating a syndrome s3 based on data received from the MEMORY array; and
error checking based on the syndrome s1 and the syndrome s3.

12. The method of claim 11 , wherein remainder steps of the error detection and correcting the data error with the second ECC circuit comprises:
generating an EN based on data received from the MEMORY array;
generating a syndrome s1{circumflex over ( )}3 based on the syndrome s1;
generating a syndrome s1 inversion based on the syndrome s1;
comparing the syndrome s1{circumflex over ( )}3 and the syndrome s3;
generating a GF multi calculation based on the syndrome s1 inversion and the comparison of the syndrome s1{circumflex over ( )}3 and the syndrome s3;
generating a check bit error correction based on the EN, the syndrome s1, and the GF multi calculation; and
writing the check bit error correction to the MEMORY array to correct the error.

13. The method of claim 10 ,

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Noguchi Hiroki
• Chih Yu-Der
• Yang Hsueh-Chih
• Osborne Randy
• Khwa Win San

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• H03M13/31

  combining coding for error detection or correction and efficient use of the spectrum (without error detection or correction H03M5/14 {, H03M5/145}) · CPC title

• H03M13/1575

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title