Circuit with swept voltage on bit line or bit line bar

Patent metadata

Field	Value
Publication number	US-12562216-B2
Application number	US-202318460155-A
Country	US
Kind code	B2
Filing date	Sep 1, 2023
Priority date	Sep 1, 2023
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An integrated circuit includes a sense amplifier connected to a bit line and a bit line bar, a first memory cell configured to store a data signal and selectively output the data signal on at least one of the bit line and the bit line bar in response to a word line signal, a first circuit connected between a first voltage terminal configured to receive a first external voltage and the bit line and having a first enable terminal configured to receive a first enable signal, wherein the first external voltage is different than the data signal, and a second circuit connected between a second voltage terminal configured to receive a second external voltage and the bit line bar and having a second enable terminal configured to receive a second enable signal, wherein the second external voltage is different than the data signal and the first external voltage.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a sense amplifier having input terminals connected to a bit line and a bit line bar; a first memory cell configured to store a data signal and selectively output the data signal on at least one of the bit line and the bit line bar in response to a word line signal; a first circuit connected between a first voltage terminal configured to receive a first external voltage and the bit line and having a first enable terminal configured to receive a first enable signal, wherein the first external voltage is different than the data signal; a second circuit connected between a second voltage terminal configured to receive a second external voltage and the bit line bar and having a second enable terminal configured to receive a second enable signal, wherein the second external voltage is different than the data signal and the first external voltage; and a memory cell array having a plurality of memory cells including the first memory cell, wherein the first memory cell is configured to be connected to the bit line and the second memory cell is configured to be connected to the bit line bar; wherein the first memory cell includes a first access control transistor connected between the bit line and a first storage node and the second memory cell includes a second access control transistor connected between the bit line bar and a second storage node, the first circuit is configured to receive the first enable signal and provide the first external voltage to the bit line, and the first access control transistor is configured to receive the word line signal and provide the data signal from the first storage node to the bit line, and the second circuit is configured to receive the second enable signal and provide the second external voltage to the bit line bar, wherein the second external voltage is swept from a low voltage to a high voltage and/or from a high voltage to a low voltage to switch states of the sense amplifier.

2 . The circuit of claim 1 , wherein the first enable signal and the second enable signal are the same enable signal.

3 . The circuit of claim 1 , wherein the first circuit is configured to receive the first enable signal and provide the first external voltage that is a high voltage to the bit line and the first access control transistor is biased off to measure leakage current of the bit line and/or the second circuit is configured to receive the second enable signal and provide the second external voltage that is a high voltage to the bit line bar and the second access control transistor is biased off to measure leakage current of the bit line bar.

4 . The circuit of claim 1 , wherein the first circuit is configured to receive the first enable signal and provide the first external voltage that is a high voltage to the bit line and the first access control transistor is biased on to measure leakage current of the first storage node and/or the second circuit is configured to receive the second enable signal and provide the second external voltage that is a high voltage to the bit line bar and the second access control transistor is biased on to measure leakage current of the second storage node.

5 . The circuit of claim 1 , wherein the first external voltage is an equalized pre-charge voltage and the second external voltage is swept from the low voltage to the high voltage and/or from the high voltage to the low voltage to switch states of the sense amplifier.

6 . The circuit of claim 1 , comprising a pre-charge and equalize circuit connected to the bit line and the bit line bar and configured to provide an equalized voltage to each of the bit line and the bit line bar in response to an active pre-charge enable signal.

7 . The circuit of claim 1 , wherein at least one of the first circuit and the second circuit is an n type pass gate, a p type pass gate, a CMOS pass gate, a multiplexer, or includes Y decoder gating.

8 . The circuit of claim 1 , wherein the first circuit includes a metal-oxide semiconductor field-effect transistor having a first drain/source terminal connected to the bit line, a second drain/source terminal configured to receive the first external voltage, and a gate terminal configured to receive the first enable signal.

9 . The circuit of claim 8 , wherein the metal-oxide semiconductor field-effect transistor is an n-channel metal-oxide semiconductor field-effect transistor.

10 . The circuit of claim 1 , wherein the second circuit includes a metal-oxide semiconductor field-effect transistor having a first drain/source terminal connected to the bit line bar, a second drain/source terminal configured to receive the second external voltage, and a gate terminal configured to receive the second enable signal.

11 . A semiconductor device, comprising:
a sense amplifier configured to be connected to a bit line and a bit line bar; a memory cell array including a plurality of memory cells, wherein a first memory cell has a first access control transistor connected to the bit line and to a first storage capacitor and a second memory cell has a second access control transistor connected to the bit line bar and to a second storage capacitor; a pre-charge and equalize circuit connected to the bit line and the bit line bar and configured to provide an equalized pre-charge voltage to each of the bit line and the bit line bar in response to an active pre-charge enable signal; a first circuit that includes a first metal-oxide semiconductor field-effect transistor having a first drain/source terminal connected to the bit line, a second drain/source terminal configured to receive a first external voltage, and a gate terminal configured to receive an enable signal; and a second circuit that includes a second metal-oxide semiconductor field-effect transistor having a third drain/source terminal connected to the bit line bar, a fourth drain/source terminal configured to receive a second external voltage, and a gate terminal configured to receive the enable signal, wherein the second drain/source terminal or the first metal-oxide semiconductor field-effect transistor is connected to a fifth metal-oxide semiconductor field-effect transistor configured to receive the first external voltage and the fourth drain/source terminal of the second metal-oxide semiconductor field-effect transistor is connected to a sixth metal-oxide semiconductor field-effect transistor is connected to a sixth external voltage.

12 . The device of claim 11 , wherein each of the first metal-oxide semiconductor field-effect transistor and the second metal-oxide semiconductor field-effect transistor is an n-channel metal-oxide semiconductor field-effect transistor.

13 . The device of claim 11 , wherein each of the first metal-oxide semiconductor field-effect transistor and the second metal-oxide semiconductor field-effect transistor is a p-channel metal-oxide semiconductor field-effect transistor.

14 . The device of claim 11 , wherein the first metal-oxide semiconductor field-effect transistor is part of a first complementary metal-oxides semiconductor pass gate and the second metal-oxide semiconductor field-effect transistor is part of a second complementary metal-oxides semiconductor pass gate.

15 . The device of claim 11 , wherein each of the fifth metal-oxide semiconductor field-effect transistor and the sixth metal-oxide semiconductor field-effect transistor is an n-channel metal-oxide semiconductor field-effect transistor.

16 . A method of operating a semiconductor device, the method comprising:
receiving a first enable signal at a first

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Chi
• Huang Chia-En
• Liu Yi-Ching
• Noguchi Hiroki
• Wang Yih

Classifications

• G11C2029/1204

  Bit line control · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C29/026

  in sense amplifiers · CPC title

• G11C29/50 Primary

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title