Memory device with write pulse trimming

Patent metadata

Field	Value
Publication number	US-12165704-B2
Application number	US-202318352127-A
Country	US
Kind code	B2
Filing date	Jul 13, 2023
Priority date	Jan 4, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

First claim

What is claimed is:

1. A method, comprising:
detecting a temperature of a memory device that includes a memory cell array, wherein the temperature of the memory device is a temperature of the memory cell array;
determining a target write pulse width based on the detected temperature of the memory device by reading a temperature dependent table; and
writing data to the memory device using the target write pulse width by generating a write pulse with the target write pulse width and writing the data to the memory device using the write pulse.

2. The method of claim 1 , wherein determining the target write pulse width based on the detected temperature of the memory device includes:
identifying the temperature of the memory device in the temperature dependent table; and
identifying the target write pulse width associated with the temperature of the memory device.

3. The method of claim 1 , wherein the temperature dependent table is generated in an initial testing procedure.

4. The method of claim 3 , wherein the initial testing procedure includes sweeping temperature, write pulse width, and voltage of the memory device.

5. The method of claim 4 , wherein the initial testing procedure includes calculating write error rates under different temperature, write pulse width, and voltage conditions.

6. The method of claim 5 , wherein the initial testing procedure includes generating the temperature dependent table based on the write error rates calculated under the different temperature, write pulse width, and voltage conditions.

7. The method of claim 6 , wherein the initial testing procedure includes storing the temperature dependent table in a storage of the memory device.

8. The method of claim 1 , wherein the temperature dependent table includes a plurality of temperature dependent tables corresponding to a plurality of applications.

9. The method of claim 1 , wherein the memory device is one of: ferroelectric random access memories (FRAMs), magnetic random access memories (MRAMs), resistive random access memories (RRAMs), and phase-change memories (PCMs).

10. A method, comprising:
detecting a temperature of a memory device;
determining a target write pulse width based on the detected temperature of the memory device; and
writing data to the memory device using the target write pulse width,
wherein the determining the target write pulse width based on the detected temperature of the memory device comprises:
reading a temperature dependent table that is generated in an initial testing procedure and stored in a storage of the memory device;
identifying the temperature of the memory device in the temperature dependent table; and
identifying the target write pulse width associated with the temperature of the memory device.

11. The method of claim 10 , wherein the initial testing procedure includes sweeping temperature, write pulse width, and voltage of the memory device.

12. The method of claim 11 , wherein the initial testing procedure includes calculating write error rates under different temperature, write pulse width, and voltage conditions.

13. The method of claim 12 , wherein the initial testing procedure includes generating the temperature dependent table based on the write error rates calculated under the different temperature, write pulse width, and voltage conditions.

14. The method of claim 10 , wherein the temperature dependent table includes a plurality of temperature dependent tables corresponding to a plurality of applications.

15. The method of claim 10 , wherein the writing data to the memory device using the target write pulse width includes:
generating a write pulse with the target write pulse width; and
writing the data to the memory device using the write pulse.

16. A memory device, comprising:
a storage device configured to store a threshold write error rate;
an error monitor configured to detect a write error rate of the memory device;
a controller configured to compare the detected write error rate to the threshold write error rate; and
a pulse generator circuit configured to increase a write pulse width if the detected write error rate is higher than the threshold write error rate, and to decrease the write pulse width if the detected write error rate is lower than the threshold write error rate, wherein the pulse generator circuit is configured to increase or decrease the write pulse width by an amount proportionate to a difference between the write error rate and the threshold write error rate.

17. The memory device of claim 16 , wherein the pulse generator circuit is configured to increase the write pulse width by:
generating a first write pulse with an increased write pulse width; and
writing data to the memory device using the first write pulse.

18. The memory device of claim 16 , wherein the pulse generator circuit is configured to decrease the write pulse width by:
generating a second write pulse with a decreased write pulse width; and
writing data to the memory device using the second write pulse.

19. The memory device of claim 16 , wherein the controller is configured to determine the difference between the write error rate and the threshold write error rate.

20. The memory device of claim 16 , wherein the memory device is one of: ferroelectric random access memories (FRAMs), magnetic random access memories (MRAMs), resistive random access memories (RRAMs), and phase-change memories (PCMs).

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Noguchi Hiroki
• Chih Yu-Der
• Wang Yih

Classifications

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title

• G11C2207/229

  Timing of a write operation · CPC title

• G11C29/022

  in I/O circuitry · CPC title