Memory interface

Patent metadata

Field	Value
Publication number	US-12517679-B2
Application number	US-202217724182-A
Country	US
Kind code	B2
Filing date	Apr 19, 2022
Priority date	Jan 12, 2022
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A memory interface circuit includes a request decoder configured to receive a command signal and an address signal. The request decoder is configured to decode the command signal and the address signal to generate a data count signal and a start address signal. A burst counter is coupled to the request decoder, and the burst counter is configured to update the data count signal after each access of a memory. An address generator is coupled to the request decoder. The address generator is configured to receive the start address signal and generate a subsequent memory address signal based on the start address signal after each access of the memory.

First claim

What is claimed is:

1 . A memory device, comprising:
a memory having memory cells; a request decoder configured to receive a command signal and an address signal, wherein the request decoder is configured to decode the command signal and the address signal to generate a data count signal, a start address signal, and a memory operation command signal; a burst counter coupled to the request decoder, wherein the burst counter includes:
a multiplexer that has a first input, a second input, and an output, wherein the multiplexer receives the data count signal at the first input and an updated counter data count signal at the second input and selectively provides a multiplexer data count signal at the output;
a counter that receives the multiplexer data count signal and provides a corresponding counter data count signal at a counter output; and
a count adjust circuit that receives the counter data count signal, updates the counter data count signal after each access of the memory, and provides the updated counter data count signal to the second input to be selectively provided at the output after each access of the memory;
an enable circuit configured to receive the counter data count signal after each access of the memory and indicate whether one or more memory access addresses remain after each access of the memory; an address generator coupled to the request decoder, wherein the address generator is configured to receive the start address signal and generate a subsequent memory address signal based on the start address signal after each access of the memory; and a command generator coupled to the request decoder, wherein the command generator is configured to receive the memory operation command signal and generate a read enable command to read data from one or more of the memory cells if the memory operation command signal includes a read command, and to generate a write enable command to write data into one or more of the memory cells if the memory operation command signal includes a write command.

2 . The memory device of claim 1 , wherein the burst counter is configured to receive a data count of 1 in the data count signal for a normal, non-burst access, and a data count of greater than 1 for a burst access.

3 . The memory device of claim 1 , wherein the burst counter is configured to increment the counter data count signal after each access of the memory.

4 . The memory device of claim 1 , further comprising a data bus coupled to the request decoder, wherein the data bus is configured to selectively output data received from the memory and/or input data to the memory based on the command signal.

5 . The memory device of claim 1 , wherein the burst counter is configured to decrement the counter data count signal after each access of the memory.

6 . The memory device of claim 1 , wherein the burst counter is configured for a burst memory access.

7 . The memory device of claim 6 , wherein the burst memory access includes a plurality of sequential memory addresses.

8 . The memory device of claim 6 , wherein the start address signal corresponds to a first memory address, and wherein the subsequent memory address signal corresponds to a second memory address.

9 . The memory device of claim 6 , wherein the address generator is configured to generate the subsequent memory address signal by incrementing or decrementing the start address signal.

10 . A memory device, comprising:
a first memory including a plurality of memory cells arranged in rows and columns, the first memory having an address input terminal, a data input terminal and a data output terminal; a data bus connected to the data input terminal and the data output terminal, wherein the data bus is configured to provide data to be written to the first memory and receive data read from the first memory; a memory interface circuit configured to selectively implement a burst memory access mode and a non-burst memory access mode, the memory interface circuit is configured to receive a command signal and generate a read enable command to read data from one or more of the plurality of memory cells if the command signal includes a read command and generate a write enable command to write data into one or more of the memory cells if the command signal includes a write command, the memory interface circuit includes an address generator having an output terminal connected to the address input terminal of the first memory, the address generator configured to receive a start address signal and generate a first memory address based on the start address signal at the output terminal, wherein the first memory is configured to access the first memory address in the burst memory access mode and in the non-burst memory access mode, and the address generator is configured to generate a second memory address based on the first memory address at the output terminal in the burst memory access mode, and wherein the memory interface circuit includes a burst counter that includes:
a multiplexer that has a first input, a second input, and an output, wherein the multiplexer receives a data count signal at the first input and an updated counter data count signal at the second input and selectively provides a multiplexer data count signal at the output;
a counter that receives the multiplexer data count signal and provides a corresponding counter data count signal; and
a count adjust circuit that receives the counter data count signal, updates the counter data count signal after each access of the memory, and provides the updated counter data count signal to the second input to be selectively provided at the output after each access of the memory; and
an enable circuit configured to receive the counter data count signal alter each access of the memory and indicate whether one or more memory access addresses remain after each access of the memory.

11 . The memory device of claim 10 , wherein the address generator is configured to generate the second memory address only in the burst memory access mode.

12 . The memory device of claim 10 , wherein the first memory address and the second memory address are sequential.

13 . The memory device of claim 10 , further comprising a second memory wherein the data bus is connected between the first memory and the second memory.

14 . The memory device of claim 10 , wherein the memory interface circuit includes a request decoder configured to receive an address signal, wherein the request decoder is configured to decode the address signal and output the start address signal to the address generator.

15 . The memory device of claim 10 , wherein a request decoder is configured to receive the command signal and generate the data count signal based on the command signal.

16 . The memory device of claim 15 , wherein the data count signal is greater than 1 in the burst memory access mode and the data count signal is 1 in the non-burst memory access mode.

17 . A method of operating a memory device, comprising:
receiving a command signal at a request decoder; decoding the command signal by the request decoder into a data count signal and a memory operation command signal, generating, by a command generator coupled to the request decoder and front the memory operation command signal, a read enable command to read data from one or more memory cells of a memory of the memory device or a write enable command to write data into the one or more memory cells of the memory; receiving the data count signal at a first input of a multiplexer in a burst counter; receiving an updated co

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Noguchi Hiroki
• Wang Yih

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title