Metal layers for a three-port bit cell
US-2019035796-A1 · Jan 31, 2019 · US
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Mojumder Niladri Narayan patents
Mojumder Niladri Narayan is listed as an inventor on 38 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Mojumder Niladri Narayan |
| Total patents | 38 |
| First publication | Apr 30, 2015 |
| Latest publication | Jan 31, 2019 |
Notable patents
Publications ranked by popularity score, then publication date.
Metal layers for a three-port bit cell
US-10141317-B2 · Nov 27, 2018 · US
Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
US-9876017-B2 · Jan 23, 2018 · US
Static random-access memory (SRAM) sensor for bias temperature instability
US-9812188-B2 · Nov 7, 2017 · US
Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods
US-9806083-B2 · Oct 31, 2017 · US
Self-aligned structure
US-9799560-B2 · Oct 24, 2017 · US
Memory device with adaptive voltage scaling based on error information
US-9786356-B2 · Oct 10, 2017 · US
Integrated circuit devices and methods
US-9721891-B2 · Aug 1, 2017 · US
Voltage scaling for holistic energy management
US-9660649-B2 · May 23, 2017 · US
Integrated circuit devices and methods
US-2017092587-A1 · Mar 30, 2017 · US
Recent patents
Latest publications not already listed above.
Metal layers for a three-port bit cell
US-2017062439-A1 · Mar 2, 2017 · US
User experience based management technique for mobile system-on-chips
US-9542518-B2 · Jan 10, 2017 · US
Integrated circuit devices and methods
US-9543248-B2 · Jan 10, 2017 · US
Three-port bit cell having increased width
US-9536596-B2 · Jan 3, 2017 · US
Metal layers for a three-port bit cell
US-9524972-B2 · Dec 20, 2016 · US
Self-aligned structure
US-2016293485-A1 · Oct 6, 2016 · US
Shared global read and write word lines
US-9455026-B2 · Sep 27, 2016 · US
Volatile memory and one-time program (OTP) compatible memory cell and programming method
US-9449709-B1 · Sep 20, 2016 · US
Static random-access memory (sram) sensor
US-2016247554-A1 · Aug 25, 2016 · US
Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation
US-9424909-B1 · Aug 23, 2016 · US
Metal layers for a three-port bit cell
US-2016240539-A1 · Aug 18, 2016 · US
Integrated circuit device including multiple via connectors and a metal structure having a ladder shape
US-2016233159-A1 · Aug 11, 2016 · US
Memory device with adaptive voltage scaling based on error information
US-2016225436-A1 · Aug 4, 2016 · US
Integrated circuit devices and methods
US-2016211216-A1 · Jul 21, 2016 · US
Static random-access memory (SRAM) array
US-9379014-B1 · Jun 28, 2016 · US
Static random access memory (sram) bit cells with wordlines on separate metal layers for increased performance, and related methods
US-2016163713-A1 · Jun 9, 2016 · US
Strapped contact in a semiconductor device
US-2016163646-A1 · Jun 9, 2016 · US
Static random access memory (sram) bit cells with wordline landing pads split across boundary edges of the sram bit cells
US-2016163714-A1 · Jun 9, 2016 · US
Shared global read and write word lines
US-2016141021-A1 · May 19, 2016 · US
Voltage scaling for holistic energy management
US-2016142054-A1 · May 19, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 38 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10B10/12 | 19 |
| H10W20/43 | 16 |
| H01L23/528 | 16 |
| H10D89/10 | 14 |
| G11C8/16 | 13 |