Integrated circuit devices and methods

Patent metadata

Field	Value
Publication number	US-9721891-B2
Application number	US-201615378633-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Jan 21, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes an aluminum oxide barrier layer. The aluminum oxide barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a first metal layer comprising aluminum;
a second metal layer including an interconnect structure, wherein the interconnect structure includes a layer of first material including aluminum;
an inter-diffusion layer including aluminum, the inter-diffusion layer in contact with the first metal layer and in contact with the layer of first material including aluminum; and
an aluminum oxide barrier layer proximate to a dielectric layer and proximate to the layer of first material including aluminum.

2. The integrated circuit device of claim 1 , further comprising a barrier layer in contact with the first metal layer and in contact with the inter-diffusion layer.

3. The integrated circuit device of claim 1 , wherein the inter-diffusion layer includes aluminum cobalt (Al 9 Co 2 ), and wherein the aluminum oxide barrier layer is proximate to the inter-diffusion layer.

4. The integrated circuit device of claim 1 , wherein the second metal layer comprises a first metal line and a second metal line separated by an airgap.

5. The integrated circuit device of claim 4 , wherein the second metal layer further includes a third metal line separated from the first metal line by a second airgap.

6. The integrated circuit device of claim 5 , wherein the airgap has a width of about 12 nanometers (nm).

7. A method of forming an integrated circuit device, the method comprising:
forming a first opening in a dielectric layer, the first opening exposing a portion of a first metal layer that includes aluminum; and
forming an inter-diffusion layer at least in part by:
selectively forming a conductive layer proximate to the portion of the first metal layer;
depositing material of a second metal layer in contact with the conductive layer, wherein the material of the second metal layer includes aluminum; and
causing the conductive layer to react with the first metal layer and material of the second metal layer to create the inter-diffusion layer in contact with the first metal layer and the second metal layer.

8. The method of claim 7 , wherein depositing the material of the second metal layer includes depositing copper-doped aluminum.

9. The method of claim 7 , wherein depositing the material of the second metal layer comprises depositing a seed layer.

10. The method of claim 7 , further comprising performing an aluminum reflow process on the second metal layer.

11. The method of claim 7 , wherein forming the first opening includes performing an in-situ H radical treatment.

12. The method of claim 7 , forming an airgap between a first metal line formed in the first opening and a second metal line formed in a second opening formed in the dielectric layer.

13. The method of claim 12 , wherein forming the airgap comprises:
depositing an etch stop layer proximate to the dielectric layer;
forming first and second openings in the etch stop layer, the first and second openings in the etch stop layer exposing first and second portions of the dielectric layer located between the first and second metal lines; and
etching the first and second portions of the dielectric layer through the first and second openings in the etch stop layer.

14. The method of claim 13 , further comprising sealing the airgap by depositing a dielectric material proximate to the etch stop layer.

15. A non-transitory computer-readable medium comprising processor-executable instructions that, when executed by a processor, cause the processor to:
initiate fabrication of an electronic device, the electronic device fabricated by:
forming a first opening in a dielectric layer, the first opening exposing a portion of a first metal layer that includes aluminum; and
forming an inter-diffusion layer at least in part by:
selectively forming a conductive layer proximate to the portion of the first metal layer;
depositing material of a second metal layer in contact with the conductive layer, wherein the material of the second metal layer includes aluminum; and
causing the conductive layer to react with the first metal layer and material of the second metal layer to create the inter-diffusion layer in contact with the first metal layer and the second metal layer.

16. The non-transitory computer-readable medium of claim 15 , wherein depositing the material of the second metal layer includes depositing copper-doped aluminum.

17. The non-transitory computer-readable medium of claim 15 , wherein depositing the material of the second metal layer comprises depositing a seed layer.

18. The non-transitory computer-readable medium of claim 15 , wherein the electronic device is further fabricated by performing an aluminum reflow process on the second metal layer.

19. The non-transitory computer-readable medium of claim 15 , wherein forming the first opening includes performing an in-situ H radical treatment.

20. The non-transitory computer-readable medium of claim 15 , wherein the electronic device is further fabricated by forming an airgap between a first metal line formed in the first opening and a second metal line formed in a second opening formed in the dielectric layer.

Assignees

• Qualcomm Inc

Inventors

• Xu Jeffrey Junhao
• Bao Junjing
• Zhu John Jianhong
• Song Stanley Seungchul
• Mojumder Niladri Narayan
• Yeap Choh Fei

Classifications

• G05B19/418

  Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] · CPC title

• B33Y50/02

  for controlling or regulating additive manufacturing processes · CPC title

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title

• H10W20/4407

  Aluminium alloys · CPC title

• H10W20/076

  in via holes or trenches · CPC title