Static random-access memory (SRAM) sensor for bias temperature instability

Patent metadata

Field	Value
Publication number	US-9812188-B2
Application number	US-201514631603-A
Country	US
Kind code	B2
Filing date	Feb 25, 2015
Priority date	Feb 25, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

First claim

What is claimed is:

1. An apparatus comprising:
an array of static random-access memory (SRAM) cells, wherein each SRAM cell of the array has a size within a target range, wherein each SRAM cell of the array of SRAM cells is configured to be initialized to a corresponding initial state based on a supply voltage received during a power-up operation of the array; and
circuitry configured to initiate a corrective action related to the array, the corrective action based on a number of the SRAM cells of the array of SRAM cells that, responsive to the power-up operation, have a particular initial state.

2. The apparatus of claim 1 , further comprising a SRAM including a plurality of SRAM cells including the array of SRAM cells, wherein the plurality of SRAM cells are substantially uniform, and wherein the corrective action accounts for degradation experienced by the array of SRAM cells.

3. The apparatus of claim 1 , wherein the size of each SRAM cell corresponds to a pull-up transistor gate width, a pull-down transistor gate width, a pass gate transistor gate width, or a combination thereof, wherein the corresponding initial state of each SRAM cell comprises a “01” state or a “10” state, and wherein the particular initial state comprises the “01” state.

4. The apparatus of claim 1 , wherein the corrective action includes adjusting a wordline under-drive value applied during a read operation performed at the array of SRAM cells.

5. The apparatus of claim 1 , wherein the corrective action includes adjusting a read current applied during a read operation.

6. The apparatus of claim 1 , wherein the target range corresponds to a manufacturing tolerance or an operating parameter tolerance.

7. The apparatus of claim 1 , wherein each SRAM cell of the array of SRAM cells has substantially the same pull-up to pull-down ratio.

8. The apparatus of claim 1 , wherein each SRAM cell of the array of SRAM cells has substantially the same pull-up to pass gate ratio.

9. The apparatus of claim 1 , wherein the array of SRAM cells is configured to have a particular statistical probability of the SRAM cells of the array having the particular initial state responsive to the power-up operation.

10. The apparatus of claim 1 , further comprising a counter configured to count the number of the SRAM cells of the array that have the particular initial state, wherein a first initial state of a first SRAM cell is determined based on a logical value of a single node of the first SRAM cell, and wherein the first initial state corresponds to a “01” state.

11. The apparatus of claim 1 , wherein the corrective action includes adjusting the supply voltage provided to the array of SRAM cells, and wherein the corrective action is associated with compensating for bias temperature instability (BTI).

12. The apparatus of claim 1 , wherein the circuitry is configured to:
compare the number of the SRAM cells that have the particular initial state to a threshold value; and
initiate the corrective action responsive to the number being greater than or equal to the threshold value.

13. The apparatus of claim 1 , wherein the circuitry is configured to program each of the SRAM cells of the array of SRAM cells to the same state subsequent to determining the number of SRAM cells having the particular initial state.

14. The apparatus of claim 1 , wherein the array and the circuitry are included in a mobile device.

15. The apparatus of claim 1 , further comprising detection circuitry configured to determine the number of the SRAM cells having the particular initial state responsive to the power-up operation.

16. The apparatus of claim 1 , wherein the corrective action includes adjusting a supply voltage provided to the SRAM, adjusting a wordline under-drive value applied during a read operation, adjusting a read current applied during the read operation, modifying an error correction scheme associated with the SRAM, or a combination thereof, and wherein the corrective action is configured to compensate for aging associated with usage of the array.

17. An apparatus comprising:
a static random-access memory (SRAM), wherein each SRAM cell of the SRAM is configured to be initialized to a corresponding initial state based on a supply voltage received during a power-up operation of the SRAM; and
circuitry configured to initiate a corrective action based on a number of the SRAM cells of the SRAM that, responsive to the power-up operation, have a particular initial state.

18. The apparatus of claim 17 , further comprising:
detection circuitry configured to read each of the SRAM cells of the SRAM to determine the number of the SRAM cells that have the particular initial state responsive to the power-up operation; and
a common supply, wherein the common supply includes a power supply circuit configured to provide the supply voltage to the SRAM responsive to the power-up operation.

19. The apparatus of claim 18 , wherein the common supply is configured to detect a power-on request and to provide the supply voltage to the SRAM responsive to the power-on request, and wherein the power-up operation of the SRAM corresponds to a transition of the SRAM cells from an unpowered state to a powered state.

20. The apparatus of claim 18 , wherein the common supply is configured to perform the corrective action, and wherein the corrective action adjusts a value of the supply voltage provided by the common supply.

21. The apparatus of claim 17 , wherein the corrective action includes modifying an error correction scheme associated with the SRAM.

22. A method comprising:
during a power-up operation of a static random-access memory (SRAM), initializing each SRAM cell of an array of SRAM cells of the SRAM to a corresponding initial state based on a supply voltage;
determining a number of the SRAM cells of the array of SRAM cells having a particular initial state responsive to detecting the power-up operation; and
initiating a corrective action based on the number of the SRAM cells having the particular initial state.

23. The method of claim 22 , further comprising programming each of the SRAM cells of the array to the same state subsequent to determining the number of the SRAM cells having the particular initial state, wherein data is not written to the SRAM cells during a time period between the power-up operation and programming each of the SRAM cells of the array to the same state.

24. The method of claim 22 , further comprising:
comparing the number of the SRAM cells to a threshold; and
in response to the number of the SRAM cells being greater than or equal to the threshold, determining a voltage shift amount, wherein the corrective action adjusts the supply voltage provided to the SRAM based on the voltage shift amount.

25. The method of claim 24 , wherein adjusting the supply voltage comprises increasing the supply voltage by an amount associated with the voltage shift amount, and wherein the corrective action is applied to each of the SRAM cells of the array of SRAM cells.

26. The method of claim 24 , further comprising:
detecting a second power-up operation subsequent to the supply voltage being adjusted;
determining a second number of the SRAM cells of the array having the particular initial state responsive to the second power-up operation;
comparing the second number of the SRAM cells to a second threshold;
in response to the second number of the SRAM cells bei

Assignees

• Qualcomm Inc

Inventors

• Mojumder Niladri Narayan
• Wang Zhongze
• Chen Xiaonan
• Song Stanley Seungchul
• Yeap Choh Fei

Classifications

• G11C7/20 Primary

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C2029/5002

  Characteristic · CPC title

• G11C2029/0407

  on power on · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title