Metal layers for a three-port bit cell

Patent metadata

Field	Value
Publication number	US-9524972-B2
Application number	US-201514620480-A
Country	US
Kind code	B2
Filing date	Feb 12, 2015
Priority date	Feb 12, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

First claim

What is claimed is:

1. An apparatus comprising:
a first metal layer coupled to a bit cell;
a third metal layer including a write word line coupled to the bit cell; and
a second metal layer between the first metal layer and the third metal layer, the second metal layer including two read word lines coupled to the bit cell.

2. The apparatus of claim 1 , wherein the bit cell is a three-port bit cell.

3. The apparatus of claim 1 , wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process.

4. The apparatus of claim 3 , wherein the semiconductor manufacturing process comprises a 10 nm process.

5. The apparatus of claim 3 , wherein the semiconductor manufacturing process comprises a 7 nm process.

6. The apparatus of claim 1 , wherein the first metal layer, the second metal layer, and the third metal layer are patterned using a self-aligned double patterning (SADP) process.

7. The apparatus of claim 1 , further comprising:
a first via connecting the first metal layer to the second metal layer; and
a second via connecting the second metal layer to the third metal layer.

8. The apparatus of claim 1 , wherein the second metal layer does not include jogs.

Assignees

• Qualcomm Inc

Inventors

• Mojumder Niladri Narayan
• Chaba Ritu
• Liu Ping
• Song Stanley Seungchul
• Wang Zhongze
• Yeap Choh Fei

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title