Static random-access memory (sram) sensor

Patent metadata

Field	Value
Publication number	US-2016247554-A1
Application number	US-201514631603-A
Country	US
Kind code	A1
Filing date	Feb 25, 2015
Priority date	Feb 25, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

First claim

1 . An apparatus comprising:
an array of static random-access memory (SRAM) cells, wherein each SRAM cell of the array has a size within a target range; and circuitry configured to initiate a corrective action related to the array, the corrective action based on a number of SRAM cells of the array that have a particular state.

2 . The apparatus of claim 1 , further comprising a SRAM including a plurality of SRAM cells including the array, wherein the plurality of SRAM cells are substantially uniform.

3 . The apparatus of claim 1 , wherein the size corresponds to a pull-up transistor gate width, a pull-down transistor gate width, a pass gate transistor gate width, or a combination thereof.

4 . The apparatus of claim 1 , wherein the corrective action includes adjusting a wordline under-drive value applied during a read operation performed at the array.

5 . The apparatus of claim 1 , wherein the corrective action includes adjusting a read current applied during a read operation.

6 . The apparatus of claim 1 , wherein the target range corresponds to a manufacturing tolerance or an operating parameter tolerance.

7 . The apparatus of claim 1 , wherein each SRAM cell of the array has substantially the same pull-up to pull-down ratio.

8 . The apparatus of claim 1 , wherein each SRAM cell of the array has substantially the same pull-up to pass gate ratio.

9 . The apparatus of claim 1 , wherein the array is configured to have a particular statistical probability of the array having the particular state as an initial state responsive to a power-up operation.

10 . The apparatus of claim 1 , wherein the particular state of a first SRAM cell is determined based on a logical value of a single node of the first SRAM cell.

11 . The apparatus of claim 1 , wherein the corrective action includes adjusting a supply voltage to the array.

12 . The apparatus of claim 1 , wherein the circuitry is configured to compare the number to a threshold value, and to initiate the corrective action responsive to the number being greater than or equal to the threshold value.

13 . The apparatus of claim 1 , wherein the circuitry is configured to program each SRAM cell of the array to the same state subsequent to determining the number of SRAM cells having the particular state.

14 . The apparatus of claim 9 , wherein the particular statistical probability is fifty percent.

15 . The apparatus of claim 1 , further comprising detection circuitry configured to determine the number of SRAM cells of the array having the particular state, wherein the number of SRAM cells have the particular state responsive to a voltage being provided to the SRAM.

16 . An apparatus comprising:
a static random-access memory (SRAM); and circuitry configured to initiate a corrective action based on a number of SRAM cells that have a particular state responsive to a power-up of the SRAM.

17 . The apparatus of claim 16 , further comprising:
a detection circuitry configured to determine the number of SRAM cells that have the particular state responsive to the power-up of the SRAM; and a common supply, wherein the common supply includes a power supply circuit configured to provide a voltage to the SRAM.

18 . The apparatus of claim 17 , wherein the common supply is configured to detect a power-on request and to supply the voltage to the SRAM responsive to the power-on request.

19 . The apparatus of claim 17 , wherein the common supply is configured to perform the corrective action, and wherein the corrective action adjusts a value of the voltage provided by the common supply.

20 . The apparatus of claim 16 , wherein the corrective action includes modifying an error correction scheme.

21 . A method comprising:
detecting a power-up of a static random-access memory (SRAM); determining a number of SRAM cells of an array of SRAM cells of the SRAM having a particular state responsive to the power-up; and initiating a corrective action based on the number of SRAM cells having the particular state.

22 . The method of claim 21 , further comprising programming each SRAM cell of the array to the same state subsequent to determining the number of SRAM cells having the particular state.

23 . The method of claim 21 , further comprising:
comparing the number of SRAM cells to a threshold; and in response to the number of SRAM cells being greater than or equal to the threshold, determining a voltage shift amount, wherein the corrective action adjusts a supply voltage to the SRAM based on the voltage shift amount.

24 . The method of claim 23 , further comprising increasing the supply voltage by an amount associated with the voltage shift amount.

25 . The method of claim 23 , further comprising:
detecting a second power-up of the SRAM subsequent to the supply voltage being adjusted; determining a second number of SRAM cells of the array having a particular state responsive to the second power-up; comparing the second number of SRAM cells to a second threshold; in response to the second number of SRAM cells being greater than or equal to the second threshold, determining a second voltage shift amount; and increasing the supply voltage by a second amount associated with the second voltage shift amount.

26 . An apparatus comprising:
a static random-access memory (SRAM) including an on-chip sensor; a controller configured to determine an estimated amount of voltage shift of a transistor threshold voltage based on measurement of state values of the on-chip sensor; and a circuit configured to adjust a supply voltage provided to the SRAM based on the estimated amount of voltage shift.

27 . The apparatus of claim 26 , wherein the circuit includes a power management integrated circuit (PMIC).

28 . The apparatus of claim 27 , wherein the controller is configured to generate an output signal based on the estimated amount of voltage shift, and wherein the PMIC is configured to adjust the supply voltage responsive to the output signal.

29 . The apparatus of claim 26 , wherein the on-chip sensor includes multiple SRAM cells of the SRAM.

30 . The apparatus of claim 26 , wherein the estimated amount of voltage shift is determined based on a number of SRAM cells of the on-chip sensor that have a particular state responsive to the circuit providing the supply voltage to the SRAM during a power-up operation associated with the SRAM.

Assignees

• Qualcomm Inc

Inventors

• Mojumder Niladri Narayan
• Wang Zhongze
• Chen Xiaonan
• Song Stanley Seungchul
• Yeap Choh Fei

Classifications

• G11C29/021

  in voltage or current generators · CPC title

• G11C2029/5002

  Characteristic · CPC title

• G11C2029/0407

  on power on · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title