Shared global read and write word lines

Patent metadata

Field	Value
Publication number	US-9455026-B2
Application number	US-201414546980-A
Country	US
Kind code	B2
Filing date	Nov 18, 2014
Priority date	Nov 18, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

First claim

What is claimed is:

1. An apparatus comprising:
an array of bit cells comprising a first row of bit cells and a second row of bit cells;
a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells; and
a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells;
wherein the first global read word line and the second global read word line are located in a common metal layer.

2. The apparatus of claim 1 , further comprising a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells, wherein the global write word line is located in the common metal layer.

3. The apparatus of claim 2 , further comprising row select logic that is configured to:
receive a selection signal;
couple the first global read word line, the second global read word line, and the global write word line to the first row of bit cells if the selection signal has a first logical value; and
couple the first global read word line, the second global read word line, and the global write word line to the second row of bit cells if the selection signal has a second logical value.

4. The apparatus of claim 1 , wherein the common metal layer is a fourth metal layer.

5. The apparatus of claim 1 , wherein the array of bit cells is manufactured using a semiconductor manufacturing process of less than 14 nanometers (nm).

6. The apparatus of claim 5 , wherein the semiconductor manufacturing process is a 10 nm process.

7. The apparatus of claim 6 , wherein a pitch of the first global read word line is approximately 80 nm, wherein a pitch of the second global read word line is approximately 80 nm, and wherein a pitch of a global write word line is approximately 80 nm.

8. The apparatus of claim 5 , wherein the semiconductor manufacturing process is a 7 nm process.

9. The apparatus of claim 2 , further comprising:
a first local read word line coupled to the first row of bit cells, the first local read word line formed in a second metal layer;
a second local read word line coupled to the first row of bit cells, the second local read word line formed in the second metal layer; and
a first local write word line coupled to the first row of bit cells, the first local write word line formed in a third metal layer.

10. The apparatus of claim 9 , further comprising:
a third local read word line coupled to the second row of bit cells, the third local read word line formed in the second metal layer;
a fourth local read word line coupled to the second row of bit cells, the fourth local read word line formed in the second metal layer; and
a second local write word line coupled to the second row of bit cells, the second local write word line formed in the third metal layer.

11. The apparatus of claim 1 , wherein the first row of bit cells includes a three-port static random access memory (SRAM) bit cell.

12. A method comprising:
receiving, at row select logic, a selection signal;
coupling a first global read word line and a second global read word line to a first row of bit cells if the selection signal has a first logical value; and
coupling the first global read word line and the second global read word line to a second row of bit cells if the selection signal has a second logical value;
wherein the first global read word line and the second global read word line are located in a common metal layer.

13. The method of claim 12 , further comprising:
coupling a global write word line to the first row of bit cells if the selection signal has the first logical value; and
coupling the global write word line to the second row of bit cells if the selection signal has the second logical value;
wherein the global write word line is located in the common metal layer.

14. The method of claim 12 , wherein the common metal layer is a fourth metal layer.

15. The method of claim 12 , wherein the first row of bit cells and the second row of bit cells are manufactured using a semiconductor manufacturing process of less than 14 nanometers (nm).

16. The method of claim 15 , wherein the semiconductor manufacturing process is a 7 nm process or a 10 nm process.

17. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to:
initiate coupling a first global read word line and a second global read word line to a first row of bit cells if a received selection signal has a first logical value; and
initiate coupling the first global read word line and the second global read word line to a second row of bit cells if the received selection signal has a second logical value;
wherein the first global read word line and the second global read word line are located in a common metal layer.

18. The non-transitory computer-readable medium of claim 17 , further comprising instructions that, when executed by the processor, cause the processor to:
initiate coupling a global write word line to the first row of bit cells if the received selection signal has the first logical value; and
initiate coupling the global write word line to the second row of bit cells if the received selection signal has the second logical value;
wherein the global write word line is located in the common metal layer.

19. The non-transitory computer-readable medium of claim 17 , wherein the common metal layer is a fourth metal layer.

20. The non-transitory computer-readable medium of claim 17 , wherein the first row of bit cells and the second row of bit cells are manufactured using a manufacturing process of less than 14 nanometers (nm).

21. The non-transitory computer-readable medium of claim 17 , wherein the first row of bit cells includes a three-port static random access memory (SRAM) bit cell.

22. The non-transitory computer-readable medium of claim 21 , wherein the three-port SRAM bit cell includes a first read port, a second read port, and a write port, wherein a first local read word line couples the first global read word line to the first read port, wherein a second local read word line couples the second global read word line to the second read port, and wherein a local write word line couples a global write word line to the write port, and wherein the first local read word line and the second local read word line are located in a second metal layer, and wherein the local write word line is located in a third metal layer.

23. An apparatus comprising:
first means for performing a read operation configured to be selectively coupled to a first row of bit cells and to a second row of bit cells; and
second means for performing the read operation configured to be selectively coupled to the first row of bit cells and to the second row of bit cells;
wherein the first means for performing the read operation and the second means for performing the read operation are located in a common metal layer.

24. The apparatus of claim 23 , further comprising means for performing a write operation configured to be selectively coupled to the first row of bit cells and to the second row of bit cells, wherein the means for performing the write operation is located in the common metal layer.

25. The apparatus of claim 23 , wherein the common metal layer is a fourth metal layer.

26. The apparatus of claim 24 , wherein the fir

Assignees

• Qualcomm Inc

Inventors

• Mojumder Niladri Narayan
• Song Stanley Seungchul
• Wang Zhongze
• Liu Ping
• Rim Kern
• Yeap Choh Fei

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• G11C8/14 Primary

  Word line organisation; Word line lay-out · CPC title

• H01L27/0688

  Electricity · mapped topic

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title