Metal layers for a three-port bit cell

Patent metadata

Field	Value
Publication number	US-10141317-B2
Application number	US-201615347530-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Feb 12, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

First claim

What is claimed is:

1. A method comprising:
patterning a first metal layer at a bit cell;
patterning a second metal layer between the first metal layer and a third metal layer, the second metal layer including two read word lines coupled to the bit cell; and
patterning the third metal layer, the third metal layer including a write word line coupled to the bit cell.

2. The method of claim 1 , wherein the bit cell is a three-port bit cell.

3. The method of claim 1 , wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process.

4. The method of claim 3 , wherein the semiconductor manufacturing process comprises a 10 nm process.

5. The method of claim 3 , wherein the semiconductor manufacturing process comprises a 7 nm process.

6. The method of claim 1 , wherein the first metal layer, the second metal layer, and the third metal layer are patterned using a self-aligned double patterning (SADP) process.

7. The method of claim 1 , further comprising:
forming a first via, the first via connecting the first metal layer to the second metal layer; and
forming a second via, the second via connecting the second metal layer to the third metal layer.

8. The method of claim 1 , wherein the second metal layer does not include jogs.

9. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to:
initiate patterning of a first metal layer at a bit cell;
initiate patterning of a second metal layer between the first metal layer and a third metal layer, the second metal layer including two read word lines coupled to the bit cell; and
initiate patterning of the third metal layer, the third metal layer including a write word line coupled to the bit cell.

10. The non-transitory computer-readable medium of claim 9 , wherein the bit cell is a three-port bit cell.

11. The non-transitory computer-readable medium of claim 9 , wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process.

12. The non-transitory computer-readable medium of claim 11 , wherein the semiconductor manufacturing process comprises a 10 nm process.

13. The non-transitory computer-readable medium of claim 11 , wherein the semiconductor manufacturing process comprises a 7 nm process.

14. The non-transitory computer-readable medium of claim 9 , wherein the first metal layer, the second metal layer, and the third metal layer are patterned using a self-aligned double patterning (SADP) process.

15. The non-transitory computer-readable medium of claim 9 , further comprising instructions that, when executed by the processor, cause the processor to:
form a first via, the first via connecting the first metal layer to the second metal layer; and
form a second via, the second via connecting the second metal layer to the third metal layer.

16. The non-transitory computer-readable medium of claim 9 , wherein the second metal layer does not include jogs.

17. The non-transitory computer-readable medium of claim 9 , wherein the bit cell is included in a static random access memory (SRAM) device.

Assignees

• Qualcomm Inc

Inventors

• Mojumder Niladri Narayan
• Chaba Ritu
• Liu Ping
• Song Stanley Seungchul
• Wang Zhongze
• Yeap Choh Fei

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic