Seismic event displacement mitigation
US-12553489-B2 · Feb 17, 2026 · US
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Lin Ming-Yi patents
Lin Ming-Yi is listed as an inventor on 32 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lin Ming-Yi |
| Total patents | 32 |
| First publication | Feb 26, 2015 |
| Latest publication | Feb 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Integrated Circuit Layouts with Fill Feature Shapes
US-2025315588-A1 · Oct 9, 2025 · US
Integrated circuit layouts with fill feature shapes
US-12393759-B2 · Aug 19, 2025 · US
Seismic event displacement mitigation
US-2025230851-A1 · Jul 17, 2025 · US
Integrated Circuit Layouts with Fill Feature Shapes
US-2022277128-A1 · Sep 1, 2022 · US
Integrated circuit layouts with fill feature shapes
US-11334703-B2 · May 17, 2022 · US
Electronic shelf system
US-11017460-B1 · May 25, 2021 · US
Integrated Circuit Layouts with Fill Feature Shapes
US-2019005180-A1 · Jan 3, 2019 · US
Passivation structure and method of making the same
US-10049956-B2 · Aug 14, 2018 · US
Method for forming a multiple layer epitaxial layer on a wafer
US-10002761-B2 · Jun 19, 2018 · US
Recent patents
Latest publications not already listed above.
Passivation structure and method of making the same
US-2018012817-A1 · Jan 11, 2018 · US
Method of fabricating a lateral insulated gate bipolar transistor
US-9853121-B2 · Dec 26, 2017 · US
Passivation structure and method of making the same
US-9761504-B2 · Sep 12, 2017 · US
Partial SOI on power device for breakdown voltage improvement
US-9698024-B2 · Jul 4, 2017 · US
Semiconductor arrangement and formation thereof
US-9620420-B2 · Apr 11, 2017 · US
Cut mask design layers to provide compact cell height
US-9551923-B2 · Jan 24, 2017 · US
Semiconductor arrangement and formation thereof
US-2016268170-A1 · Sep 15, 2016 · US
Cell boundary layout
US-9405879-B2 · Aug 2, 2016 · US
Semiconductor arrangement and formation thereof
US-9349634-B2 · May 24, 2016 · US
Passivation structure and method of making the same
US-2016086868-A1 · Mar 24, 2016 · US
Passivation structure and method of making the same
US-9209102-B2 · Dec 8, 2015 · US
Methods And Apparatus For MEMS Structure Release
US-2015308743-A1 · Oct 29, 2015 · US
Multiple Layer Substrate
US-2015311070-A1 · Oct 29, 2015 · US
Method of fabricating a lateral insulated gate bipolar transistor
US-2015303276-A1 · Oct 22, 2015 · US
Cut mask design layers to provide compact cell height
US-2015286765-A1 · Oct 8, 2015 · US
Cell boundary layout
US-2015278428-A1 · Oct 1, 2015 · US
Semiconductor arrangement and formation thereof
US-2015243552-A1 · Aug 27, 2015 · US
Multiple layer substrate
US-9111898-B2 · Aug 18, 2015 · US
Methods and apparatus for MEMS structure release
US-9096428-B2 · Aug 4, 2015 · US
Fabrication methods of integrated semiconductor structure
US-9082789-B2 · Jul 14, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 20 |
| Taiwan Semiconductor Mfg | 13 |
| Lin Ming-Yi | 2 |
| Huang Chun-Hung | 1 |
| Lin Yu-Hsien | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/056 | 9 |
| H10D84/038 | 8 |
| G06F30/398 | 7 |
| G06F30/392 | 7 |
| H10D89/10 | 7 |