Semiconductor arrangement and formation thereof

Patent metadata

Field	Value
Publication number	US-9620420-B2
Application number	US-201615160257-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	Feb 21, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.

First claim

What is claimed is:

1. A method of forming a semiconductor arrangement comprising:
forming a first set of one or more fins and a second set of one or more fins, the first set of one or more fins spaced apart from the second set of one or more fins by a first dielectric;
forming a second dielectric over the first set of one or more fins, the second set of one or more fins, and the first dielectric;
etching a first opening in the second dielectric, the first opening extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric; and
forming a first metal connect in the first opening, the first metal connect extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric to form an electrical connection between the first set of one or more fins and the second set of one or more fins.

2. The method of claim 1 , comprising:
growing epitaxial caps over the first set of one or more fins and the second set of one or more fins to define source regions and drain regions; and
forming a dummy gate, the dummy gate extending over the first set of one or more fins and the second set of one or more fins between the source regions and the drain regions.

3. The method of claim 2 , wherein the dummy gate extends over the first dielectric.

4. The method of claim 2 , wherein the second dielectric is formed after the dummy gate is formed.

5. The method of claim 2 , wherein the second dielectric is formed over the epitaxial caps.

6. The method of claim 2 , comprising:
replacing the dummy gate with a gate; and
forming a third dielectric over the second dielectric and the gate.

7. The method of claim 6 , wherein:
the etching comprises etching the third dielectric and the first opening is defined by the second dielectric and the third dielectric, and
the method comprises etching a second opening in the third dielectric over the gate.

8. The method of claim 7 , wherein the first opening and the second opening are formed concurrently using a single mask.

9. The method of claim 7 , comprising:
forming a second metal connect in the second opening.

10. The method of claim 1 , comprising:
forming a gate extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric.

11. The method of claim 10 , comprising:
forming a third dielectric over the second dielectric and the gate.

12. The method of claim 11 , wherein the etching comprises etching the third dielectric and the first opening is defined by the second dielectric and the third dielectric.

13. The method of claim 12 , comprising:
etching a second opening in the third dielectric over the gate; and
forming a second metal connect in the second opening.

14. A method of forming a semiconductor arrangement comprising:
forming a first set of one or more fins and a second set of one or more fins, the first set of one or more fins spaced apart from the second set of one or more fins by a first dielectric;
forming a second dielectric over the first set of one or more fins, the second set of one or more fins, and the first dielectric;
forming a third dielectric over the first set of one or more fins, the second set of one or more fins, the first dielectric, and the second dielectric;
etching a first opening in the second dielectric and the third dielectric, the first opening extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric;
etching a second opening in the third dielectric, the second opening extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric; and
forming a first metal connect in the first opening and a second metal connect in the second opening.

15. The method of claim 14 , comprising:
forming a gate prior to forming the third dielectric, wherein the second opening is etched in a portion of the third dielectric overlying the gate.

16. The method of claim 15 , wherein the gate extends over the first set of one or more fins, the second set of one or more fins, and the first dielectric.

17. The method of claim 14 , wherein the second opening does not extend into the second dielectric.

18. The method of claim 14 , comprising:
forming a dummy gate, the dummy gate extending over the first set of one or more fins, the second set of one or more fins, and the first dielectric, wherein the second dielectric is formed around the dummy gate.

19. A method of forming a semiconductor arrangement comprising:
forming a first set of one or more fins and a second set of one or more fins, the first set of one or more fins spaced apart from the second set of one or more fins by a first dielectric;
forming a dummy gate;
forming a second dielectric around the dummy gate and over the first set of one or more fins, the second set of one or more fins, and the first dielectric;
replacing the dummy gate with a gate;
forming a third dielectric over the second dielectric and the gate;
etching a first opening in the second dielectric and the third dielectric;
etching a second opening in a portion of the third dielectric overlying the gate; and
forming a first metal connect in the first opening and a second metal connect in the second opening.

20. The method of claim 19 , comprising growing epitaxial caps over the first set of one or more fins and the second set of one or more fins to define source regions and drain regions, wherein the first metal connect contacts a plurality of the epitaxial caps and the second metal connect contacts the gate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Chen-Hung
• Lin Chie-Luan
• Lin Ming-Yi
• Wang Yen-Sen
• Ting Jyh-Kang

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title