Passivation structure and method of making the same

Patent metadata

Field	Value
Publication number	US-10049956-B2
Application number	US-201715700476-A
Country	US
Kind code	B2
Filing date	Sep 11, 2017
Priority date	Jun 29, 2012
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

First claim

What is claimed is:

1. A method of making a passivation structure, the method comprising:
forming a doped dielectric layer over a bottom dielectric layer, wherein forming the doped dielectric layer includes varying a dopant concentration of the doped dielectric layer as a distance from the bottom dielectric layer increases; and
forming a top dielectric layer over the doped dielectric layer.

2. The method of claim 1 , wherein the forming the doped dielectric layer includes sub-atmospheric pressure chemical vapor deposition (SACVD).

3. The method of claim 2 , wherein the forming the doped dielectric layer includes using tetraethyl orthosilicate (TEOS).

4. The method of claim 1 , wherein the forming the doped dielectric layer includes introducing the dopant concentration after formation of a dielectric layer.

5. The method of claim 1 , wherein the forming the doped dielectric includes varying the dopant concentration in a single tool by changing a flow rate of dopant material.

6. The method of claim 1 , wherein the forming the doped dielectric layer includes varying the dopant concentration of phosphorus.

7. The method of claim 1 , further comprising:
forming a molding compound layer over the top dielectric layer.

8. A method of fabricating a semiconductor device, the semiconductor device comprising:
forming a passivation structure, the forming the passivation structure including:
forming a doped dielectric layer over a bottom dielectric layer, wherein the forming the doped dielectric layer comprises:
depositing a first doped layer having a first dopant concentration;
depositing a second doped layer having a second dopant concentration over the first doped layer; and
depositing a third doped layer having a third dopant concentration over the second doped layer, wherein the third dopant concentration is different from at least one of the first dopant concentration and the second dopant concentration; and

forming a top dielectric layer over the doped dielectric layer.

9. The method of claim 8 , further comprising:
forming the bottom dielectric layer, wherein during the forming the bottom dielectric layer a dopant is not intentionally introduced.

10. The method of claim 8 , wherein the first dopant concentration and the second dopant concentration are of a p-type dopant.

11. The method of claim 8 , wherein the first dopant concentration and the second dopant concentration are of an n-type dopant.

12. The method of claim 8 , wherein the first dopant concentration and the second dopant concentration are between about 1% and about 10% by weight.

13. The method of claim 8 , wherein the depositing the first doped layer and the depositing the second doped layer are performed in a same tool.

14. The method of claim 13 , wherein the same tool varies a flow rate of dopant between depositing of the first doped layer and the depositing of the second doped layer.

15. The method of claim 8 , wherein the first dopant concentration is higher than the second dopant concentration.

16. A method of fabricating a semiconductor device, the semiconductor device comprising:
disposing an inter layer dielectric (ILD) layer and a metal layer over a substrate; and
forming a passivation structure over the ILD layer and the metal layer, wherein the forming the passivation structure includes:
depositing a bottom dielectric layer;
forming a doped dielectric layer over the bottom dielectric layer, wherein the forming the doped dielectric layer includes varying one of an n-type dopant concentration or a p-type dopant concentration during the forming the doped dielectric layer; and
forming a top dielectric layer over the doped dielectric layer.

17. The method of claim 16 , wherein the forming the doped dielectric layer includes increasing the one of the n-type dopant concentration or the p-type dopant concentration as a distance from the bottom dielectric layer increases.

18. The method of claim 16 , wherein the depositing the bottom dielectric layer includes depositing an undoped or unintentionally doped dielectric material and wherein the forming the top dielectric layer includes depositing another undoped or unintentionally doped dielectric material.

19. The method of claim 16 , further comprising:
depositing a molding compound layer over the top dielectric layer.

20. The method of claim 19 , further comprising:
moving mobile ions from the molding compound layer through the doped dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Cheng-Chi
• Hung Hsuan-Hui
• Huang Kun-Ming
• Lin Ming-Yi

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/683

  carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

• H10P14/60

  of insulating materials · CPC title