Cell boundary layout

Patent metadata

Field	Value
Publication number	US-9405879-B2
Application number	US-201414231858-A
Country	US
Kind code	B2
Filing date	Apr 1, 2014
Priority date	Apr 1, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.

First claim

What is claimed is:

1. A method, comprising:
using an electronic design automation (EDA) design window displayed on a monitor to create a graphical representation used to form an integrated circuit (IC);
forming first and second standard cells within the graphical representation, which respectively have first and second layout features, wherein the first and second standard cells abut along a cell boundary so that the first and second layout features are separated over the cell boundary by a non-zero distance that is less than a minimum distance defined by a design rule; and
automatically modifying the first and second layout features by merging the first and second layout features to extend over the cell boundary so that the first and second layout features are not separated by a distance that is less than the minimum distance.

2. The method of claim 1 , wherein the first and second layout features are formed on a first design layer, and further comprising:
covering a boundary region over abutted edges of the first and second standard cells with a marker shape formed on a second design layer; and
modifying layout features that are formed on the first design layer, fail the design rule, and are covered by the marker shape.

3. The method of claim 2 , further comprising:
identifying a design rule fail with a layout verification tool, wherein the layout verification tool is configured to ignore identification of design rule fails in regions of the graphical representation of the IC that are covered by the marker shape.

4. The method of claim 1 , wherein the first and second layout features both comprise cut shapes, and wherein the merging removes portions of the first and second layout features that the cut shapes overlap.

5. The method of claim 1 , further comprising:
removing portions of the merged first and second layout features so that a resulting merged shape comprises an area of a single contact, or a total combined area of both contacts.

6. The method of claim 1 , wherein the first or second layout feature comprises an active area of a semiconductor device, a metal layer configured to connect to the semiconductor device, or a contact that connects the semiconductor device to the metal layer.

7. The method of claim 1 , wherein modifying the graphical representation of the IC further comprises adding a design feature at a second level of design hierarchy, which is above a first level of design hierarchy of the first and second standard cells.

8. The method of claim 1 , wherein the graphical representation of the IC comprises graphical layout data in CIF, OASIS, GDS, GDSII, or GL1 format.

9. The method of claim 1 , further comprising:
forming a blocking marker shape over the cell boundary, wherein the blocking marker shape has ends that abut ends of the first and second layout features; and
wherein the merging of the first and second layout features is in a space underlying the blocking marker shape.

10. The method of claim 1 , wherein merging the first and second layout features comprises:
removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.

11. The method of claim 10 , further comprising:
not removing portions of layout features covered by a contact.

12. The method of claim 1 , wherein modifying the first or second layout features comprises:
shifting edges of the first and second layout features that face one-another away from one another so that a resulting distance between the first and second layout features is greater than the minimum distance.

13. An electronic design automation (EDA) tool arrangement, comprising:
a design window, displayed on a monitor, configured to create a graphical representation used to form an integrated circuit (IC);
an automated layout tool, coupled to the design window and configured to:
form first and second standard cells within the graphical representation, which respectively have first and second layout features, wherein the first and second standard cells abut along a cell boundary so that the first and second layout features are separated over the cell boundary by a non-zero distance that is less than a minimum distance defined by a design rule; and
automatically modify the first or second layout feature so that the first and second layout features are not separated by a distance that is less than the minimum distance by merging the first and second layout features to form a single layout feature that extends over the cell boundary.

14. The EDA tool arrangement of claim 13 , further comprising a layout verification tool is configured to:
report fails to a first set of design rules to the design window for layout features that are not covered by a marker shape;
report fails to a second set of design rules to the design window for layout features that are covered by the marker shape; and
report fails to the first set of design rules to the automated layout tool for layout features that are covered by the marker shape.

15. The EDA tool arrangement of claim 14 , wherein the automated layout tool is configured to modify layout features that are covered by the marker shape that fail the first set of design rules so that they satisfy the first set of design rules.

16. A method, comprising:
providing an electronic design automation (EDA) design window displayed on a monitor to create a graphical representation used to form an integrated circuit (IC);
forming a first layout feature within a first standard cell located in the graphical representation used to form an integrated circuit (IC);
forming a second layout feature within a second standard cell located in the graphical representation, wherein the first and second standard cells abut along a cell boundary so that the first and second layout features are separated by a non-zero distance that is less than a minimum distance defined by a design rule; and
automatically merging the first and second layout features to form a single layout feature that extends over the cell boundary, thereby eliminating a distance between the first layout feature and the second layout feature that is less than the minimum distance.

17. The method of claim 16 , further comprising:
forming a blocking marker shape over the cell boundary, wherein the blocking marker shape has ends that abut ends of the first and second layout features; and
merging the first and second layout features in a space underlying the blocking marker shape.

18. The method of claim 16 , further comprising:
identifying a design rule fail based on the design rule with a layout verification tool, wherein the layout verification tool is configured to ignore identification of design rule fails in regions of the graphical representation of the IC that are covered by a marker shape.

19. The method of claim 16 , further comprising:
removing portions of the merged first and second layout features so that a resulting merged shape comprises an area of a single contact or a total combined area of both contacts.

20. The method of claim 16 , wherein the first or second layout feature comprises an active area of a semiconductor device, a metal layer configured to connect to the semiconductor device, or a contact that connects the semiconductor device to the metal layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yen-Sen
• Chen ting yu
• Hsieh Ken-Hsien
• Lin Ming-Yi
• Lu Chen-Hung

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5068

  Physics · mapped topic