Method of fabricating a lateral insulated gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-9853121-B2
Application number	US-201514790062-A
Country	US
Kind code	B2
Filing date	Jul 2, 2015
Priority date	Jul 6, 2012
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.

First claim

What is claimed is:

1. A method of fabricating a transistor, the method comprising:
doping a first well in a silicon layer of a substrate, wherein the substrate has a first type of conductivity, and the first well and the silicon layer have a second type of conductivity;
doping a second well and a third well having the first type of conductivity in the silicon layer, the first, second, and third wells being non-overlapping with one another;
thermally growing a first insulating layer over the second well between the first well and the third well and a second insulating layer over the third well;
forming a gate stack on the substrate, the gate stack having a first part overlying the first insulating layer and a second part overlying a portion of the third well;
forming a first source region in the third well, the first source region having the second type of conductivity;
forming a gate spacer around the gate stack;
after forming the gate spacer, doping a fourth well in the third well between the second insulating layer and the gate spacer, the fourth well having the first type of conductivity;
forming a second source region over a portion of the fourth well; and
forming a drain region in the first well.

2. The method of claim 1 , wherein forming the first source region in the third well comprises:
before gate spacer formation, implanting a lightly doped source (LDS) region having the second type of conductivity; and
after gate spacer formation, implanting a first n-type dopant at an acute angle relative to a top surface of the third well and into the third well below the gate spacer.

3. The method of claim 2 , wherein the implanting the first n-type dopant at the acute angle relative to the top surface of the third well occurs after doping the fourth well.

4. The method of claim 2 , wherein forming the first source region in the third well further comprises:
after gate spacer formation, implanting a second n-type dopant into the LDS region at a normal angle relative to the top surface of the third well and at a dose higher than the implantation forming the LDS region.

5. The method of claim 1 , wherein forming the first source region in the third well comprises:
before gate spacer formation, implanting an n-type dopant at a higher dopant concentration than a lightly doped drain (LDD) region in a low voltage transistor region on the substrate.

6. The method of claim 1 , wherein the doping the fourth well in the third well comprises implanting boron at a concentration of greater than about 2E14/cm 3 .

7. The method of claim 6 , wherein the implanting boron is at the concentration greater than about 8E14/cm 3 .

8. The method of claim 1 , wherein forming the gate stack comprises thermally growing a gate dielectric over the portion of the third well and the previously grown first insulating layer.

9. The method of claim 1 , further comprising forming contacts on the drain region, the gate stack, the first source region, and the second source region.

10. The method of claim 1 , wherein the thermally growing comprises exposing portions of the substrate to oxygen and water at a temperature of over 800 degrees Celsius.

11. A method of fabricating a semiconductor device, the method comprising:
doping a first well in a silicon layer of a substrate, the first well and the substrate having a first type of conductivity, and the silicon layer having a second type of conductivity;
thermally growing an insulating layer over a drift region in the silicon layer;
forming a gate stack overlying the insulating layer and a portion of the first well;
implanting a first source region in the first well, the first source region having the second type of conductivity;
forming a gate spacer around the gate stack;
doping a second well in the first well, the second well having the first type of conductivity, wherein doping the second well comprises aligning the doping with the gate spacer; and
implanting a second source region over a portion of the second well.

12. The method of claim 11 , wherein implanting the first source region in the first well comprises:
before gate spacer formation, implanting a lightly doped source (LDS) region having the second type of conductivity; and
after gate spacer formation, implanting a first n-type dopant at an acute angle relative to a top surface of the first well and into the first well below the gate spacer.

13. The method of claim 12 , wherein the implanting the first n-type dopant at the acute angle relative to the top surface of the first well occurs after doping the second well.

14. The method of claim 12 , wherein implanting the first source region in the first well further comprises:
after gate spacer formation, implanting a second n-type dopant into the LDS region at a normal angle relative to the top surface of the first well and at a dose higher than the implantation forming the LDS region.

15. The method of claim 11 , wherein implanting the first source region in the first well comprises:
before gate spacer formation, implanting an n-type dopant at a higher dopant concentration than a lightly doped drain (LDD) region in a low voltage transistor region on the substrate.

16. A method of fabricating a semiconductor device, the method comprising:
doping a first well in a silicon layer of a substrate, the first well and the substrate having a first type of conductivity, and the silicon layer having a second type of conductivity;
thermally growing a first insulating layer over a drift region in the silicon layer;
thermally growing a second insulating layer over the first well;
forming a gate stack overlying the first insulating layer and a portion of the first well;
implanting a first source region in the first well, the first source region having the second type of conductivity;
forming a gate spacer around the gate stack;
doping a second well in the first well, the second well having the first type of conductivity, wherein doping the second well comprises doping a first portion of the first well directly adjacent to the second insulating layer; and
after forming the gate spacer around the gate stack, implanting a second source region over a second portion of the second well and aligned with the second insulating layer.

17. The method of claim 16 , wherein implanting the first source region in the first well comprises:
before gate spacer formation, implanting a lightly doped source (LDS) region having the second type of conductivity; and
after gate spacer formation, implanting a first n-type dopant at an acute angle relative to a top surface of the first well and into the first well below the gate spacer.

18. The method of claim 17 , wherein the implanting the first n-type dopant at the acute angle relative to the top surface of the first well occurs after doping the second well.

19. The method of claim 17 , wherein implanting the first source region in the first well further comprises:
after gate spacer formation, implanting a second n-type dopant into the LDS region at a normal angle relative to the top surface of the first well and at a dose higher than the implantation forming the LDS region.

20. The method of claim 16 , wherein implanting the first source region in the first well comprises:
before gate spacer formation, implanting an n-type dopant at a higher dopant concentration than a lightly doped drain (LDD) region in a low voltage transistor region on the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Long-Shih
• Huang Kun-Ming
• Lin Ming-Yi

Classifications

• H01L29/0847

  Electricity · mapped topic

• H01L29/7393

  Electricity · mapped topic

• H01L29/66659

  Electricity · mapped topic

• H01L21/8222

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic