Partial SOI on power device for breakdown voltage improvement

Patent metadata

Field	Value
Publication number	US-9698024-B2
Application number	US-201414330092-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Dec 6, 2012
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

First claim

What is claimed is:

1. A method, comprising:
providing a bonded wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer bonding the device wafer to the handle wafer;
forming a semiconductor device, which includes a source region and a drain region which are disposed in the device wafer, wherein the intermediate oxide layer separates both the semiconductor device and the device wafer from the handle wafer; and
forming a recess in a lower surface of the handle wafer while leaving both the intermediate oxide layer and the device wafer entirely in place, thereby defining an un-recessed region and a recessed region of the handle wafer, wherein the un-recessed region has a first handle wafer thickness that is non-zero under the source region and the recessed region has a second handle wafer thickness that is non-zero under the drain region, the second handle wafer thickness being less than the first handle wafer thickness.

2. The method of claim 1 , wherein the device wafer has a first conductivity type, and wherein forming the semiconductor device in the device wafer comprises:
performing a first implant into an upper surface of the device wafer to form a well having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type;
forming a gate over the upper surface of the device wafer and over a portion of the well, wherein the gate is separated from the device wafer by a gate dielectric;
performing a second implant into the upper surface of the device wafer within the well adjacent the gate to form a first shallow doped region, which has the first conductivity type; and
performing a third implant into the upper surface of the device wafer within the well adjacent the first shallow doped region to form a second shallow doped region, which has the second conductivity type.

3. The method of claim 2 ,
wherein the second implant also forms a third shallow doped region, which has the first conductivity type, in the upper surface of the device wafer on an opposite side of the gate from the first and second shallow doped regions, to form the drain region of a laterally diffused metal oxide semiconductor (LDMOS) transistor; and
wherein the first shallow doped region forms the source region of the LDMOS transistor.

4. The method of claim 3 , wherein the recessed region extends beneath the device wafer between the gate and the drain region, and wherein the un-recessed region of the handle wafer extends beneath the source region.

5. The method of claim 2 ,
wherein the third implant also forms a third shallow doped region, which has the second conductivity type, in the upper surface of the device wafer on an opposite side of the gate from the first and second shallow doped regions, to form a collector of a laterally insulated gate bipolar transistor (LIGBT); and
wherein the well forms an emitter of the LIGBT.

6. The method of claim 5 , wherein the recessed region extends beneath the device wafer between the gate and the collector, and wherein the un-recessed region of the handle wafer extends beneath the emitter.

7. The method of claim 2 , wherein the second shallow doped region forms a body contact region to the well, and wherein the first and second shallow doped regions are connected to a same current source.

8. The method of claim 2 , wherein the source region has the first conductivity type within the well beneath a spacer formed along a sidewall of the gate.

9. The method of claim 2 , further comprising:
forming a field dielectric layer on the upper surface of the device wafer; and
forming a conductive field plate over the field dielectric layer.

10. The method of claim 2 ,
wherein the first conductivity type is n-type conductivity; and
wherein the second conductivity type is p-type conductivity.

11. The method of claim 1 , wherein forming the recessed region comprises:
coating the lower surface of the handle wafer with photoresist;
aligning the lower surface of the handle wafer with a photomask containing a pattern corresponding to the recessed region;
exposing the lower surface of the handle wafer to radiation to transfer the pattern to the photoresist; and
etching the pattern into the lower surface of the handle wafer.

12. A method, comprising:
providing a bonded wafer made up of a device wafer having a first conductivity type, a handle wafer, and an intermediate oxide layer bonding the device wafer to the handle wafer;
performing a first implant into an upper surface of the device wafer to form a well having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type;
forming a gate over the upper surface of the device wafer and over a portion of the well, wherein the gate is separated from the device wafer by a gate dielectric; and
performing a second implant into the upper surface of the device wafer within the well adjacent the gate to form a first shallow doped region, which has the first conductivity type; and
forming a recess in a lower surface of the handle wafer while leaving the device wafer entirely in place, thereby defining an un-recessed region and a recessed region of the handle wafer, wherein the un-recessed region has a first handle wafer thickness that is non-zero under a source region and the recessed region has a second handle wafer thickness that is non-zero under a drain region, the second handle wafer thickness being less than the first handle wafer thickness.

13. The method of claim 12 ,
wherein the second implant also forms a second shallow doped region, which has the first conductivity type, in the upper surface of the device wafer on an opposite side of the gate from the first shallow doped region, to form the drain region of a laterally diffused metal oxide semiconductor (LDMOS) transistor; and
wherein the first shallow doped region forms the source region of the LDMOS transistor.

14. The method of claim 13 , wherein the recessed region extends beneath the device wafer between the gate and the drain region, and wherein the un-recessed region of the handle wafer extends beneath the source region.

15. The method of claim 12 ,
wherein a third implant forms a second shallow doped region, which has the second conductivity type, in the upper surface of the device wafer on an opposite side of the gate from the first shallow doped region, to form a collector of a laterally insulated gate bipolar transistor (LIGBT); and
wherein the well forms an emitter of the LIGBT.

16. The method of claim 15 , wherein the recessed region extends beneath the device wafer between the gate and the collector, and wherein the un-recessed region of the handle wafer extends beneath the emitter.

17. A method, comprising:
providing a bonded wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer bonding the device wafer to the handle wafer;
forming a semiconductor device in an upper surface of the device wafer;
flipping the bonded wafer so that a lower surface of the handle wafer is facing upwards;
coating the lower surface of the handle wafer with photoresist;
aligning the lower surface of the handle wafer with a photomask containing a pattern, wherein the pattern is formed over all or part of the semiconductor device;
exposing the lower surface of the handle wafer to radiation to transfer the pattern to the photoresist; and
etching the pattern into the lower surface of the handle wafer while leaving both the intermediate oxide layer and the device wafer entirely in place to form an un-recessed region and

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Long-Shih
• Yang Fu-Hsiung
• Huang Kun-Ming
• Lin Ming-Yi
• Chu Paul

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title