Data processing engine tile architecture for an integrated circuit
US-12536132-B2 · Jan 27, 2026 · US
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Langer Jan patents
Langer Jan is listed as an inventor on 35 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Langer Jan |
| Total patents | 35 |
| First publication | Oct 3, 2019 |
| Latest publication | Jan 27, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Device with data processing engine array that enables partial reconfiguration
US-12105667-B2 · Oct 1, 2024 · US
Device with data processing engine array that enables partial reconfiguration
US-2024256482-A1 · Aug 1, 2024 · US
Data processing engine arrangement in a device
US-11972132-B2 · Apr 30, 2024 · US
Communicating between data processing engines using shared memory
US-11853235-B2 · Dec 26, 2023 · US
Dual mode interconnect
US-11730325-B2 · Aug 22, 2023 · US
Device with data processing engine array that enables partial reconfiguration
US-2023205726-A1 · Jun 29, 2023 · US
Multi-addressing mode for DMA and non-sequential read and write patterns
US-11669464-B1 · Jun 6, 2023 · US
Data processing engine arrangement in a device
US-2023131698-A1 · Apr 27, 2023 · US
Device with data processing engine array that enables partial reconfiguration
US-11599498-B1 · Mar 7, 2023 · US
Recent patents
Latest publications not already listed above.
Data processing engine arrangement in a device
US-11573726-B1 · Feb 7, 2023 · US
Event-based debug, trace, and profile in device with data processing engine array
US-11567881-B1 · Jan 31, 2023 · US
Memory tiles in data processing engine array
US-11520717-B1 · Dec 6, 2022 · US
Data processing engines with cascade connected cores
US-11443091-B1 · Sep 13, 2022 · US
Communicating between data processing engines using shared memory
US-2022283963-A1 · Sep 8, 2022 · US
Data processing engine tile architecture for an integrated circuit
US-2022283985-A1 · Sep 8, 2022 · US
Communicating between data processing engines using shared memory
US-11379389-B1 · Jul 5, 2022 · US
Data processing engine tile architecture for an integrated circuit
US-11372803-B2 · Jun 28, 2022 · US
Data processing engine array architecture with memory tiles
US-11336287-B1 · May 17, 2022 · US
Multi-port stream switch for stream interconnect network
US-11323391-B1 · May 3, 2022 · US
Dual mode interconnect
US-2022015588-A1 · Jan 20, 2022 · US
Dual mode interconnect
US-11113223-B1 · Sep 7, 2021 · US
Data selection network for a data processing engine in an integrated circuit
US-11061673-B1 · Jul 13, 2021 · US
Cascade streaming between data processing engines in an array
US-11016822-B1 · May 25, 2021 · US
Streaming interconnect architecture for data processing engine array
US-10990552-B1 · Apr 27, 2021 · US
Data processing engine arrangement in a device
US-10866753-B2 · Dec 15, 2020 · US
Device with data processing engine array that enables partial reconfiguration
US-10824584-B1 · Nov 3, 2020 · US
Core for a data processing engine in an integrated circuit
US-10747531-B1 · Aug 18, 2020 · US
Device with data processing engine array
US-10747690-B2 · Aug 18, 2020 · US
System-on-chip interface architecture
US-10635622-B2 · Apr 28, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Xilinx Inc | 35 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F15/7867 | 17 |
| G06F13/1663 | 14 |
| G06F15/7807 | 14 |
| G06F13/4022 | 12 |
| G06F15/7825 | 9 |