Data selection network for a data processing engine in an integrated circuit

Patent metadata

Field	Value
Publication number	US-11061673-B1
Application number	US-201815944393-A
Country	US
Kind code	B1
Filing date	Apr 3, 2018
Priority date	Apr 3, 2018
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute circuit coupled between the first register file and the MAC circuit. The second permute circuit is configured to generate a second vector by selecting a second set of output lanes from the first plurality of output lanes.

First claim

What is claimed is:

1. A core for a data processing engine (DPE), comprising:
a first register file configured to provide first register output lanes;
a second register file configured to provide second register output lanes; and
a processor, coupled to the first register file and the second register file, including:
a multiply-accumulate (MAC) circuit;
a first permute circuit coupled between the first register file and the MAC circuit, the first permute circuit coupled to each lane of the first register output lanes and not coupled to any lane of the second register output lanes, the first permute circuit being configured to generate a first vector by selecting, as first permute output lanes, a first set from the first register output lanes;
a second permute circuit coupled between the first register file and the MAC circuit, the second permute circuit coupled to each lane of the first register output lanes and not coupled to any lane of the second register output lanes, the second permute circuit being configured to generate a second vector by selecting, as second permute output lanes, a second set from the first register output lanes;
a third permute circuit coupled between the second register file and the MAC circuit, the third permute circuit coupled to each lane of the second register output lanes and not coupled to any lane of the first register output lanes, the third permute circuit being configured to generate a third vector by selecting, as third permute output lanes, a third set from the second register output lanes;
a pre-adder circuit coupled between (i) both the first permute circuit and the second permute circuit and (ii) the MAC circuit, the pre-adder circuit being configured to process the first vector received from the first permute output lanes and the second vector received from the second permute output lanes, the pre-adder circuit having pre-adder output lanes coupled to the MAC circuit; and
a special operation circuit coupled between (i) both the second permute circuit and the third permute circuit and (ii) the MAC circuit, the special operation circuit being configured to selectively output a unity value and a respective sign-extended version of the second vector received from the second permute output lanes and the third vector received from the third permute output lanes, the special operation circuit having special operation output lanes coupled to the MAC circuit.

2. The core of claim 1 , wherein the MAC circuit comprises:
a multiplier configured to process an output of the pre-adder circuit and an output of the special operation circuit;
at least one post-adder configured to process an output of the multiplier; and
an accumulator configured to process an output of the at least one post-adder.

3. The core of claim 2 , wherein the at least one post-adder comprises a first post-adder coupled to a second post-adder.

4. The core of claim 2 , further comprising:
a first multiplexer configured to select among the first permute output lanes, the second permute output lanes, and the third permute output lanes;
an upshift circuit coupled to an output of the first multiplexer; and
a second multiplexer coupled to an output of the upshift circuit and to the output of the at least one post-adder;
wherein the accumulator is further configured to process an output of the second multiplexer.

5. The core of claim 4 , wherein the first multiplexer is further configured to select among an output of a third register file in addition to the first permute circuit output lanes, the second permute circuit output lanes, and the third permute circuit output lanes.

6. The core of claim 1 , wherein the first register file and the second register file are portions of a single register file.

7. The core of claim 1 , wherein the first permute circuit, the second permute circuit, and the third permute circuit are portions of a single permute circuit.

8. The core of claim 1 , wherein a number of bits of the first permute output lanes is less than a number of bits of the first register output lanes, and a number of bits of the second permute output lanes is less than a number of bits of the first register output lanes.

9. An integrated circuit (IC), comprising:
a data processing engine (DPE) array having a plurality of DPEs, each of the plurality of DPEs including a core, the core including:
a first register file configured to provide first register output lanes;
a second register file configured to provide second register output lanes; and
a processor, coupled to the first register file and the second register file, including:
a multiply-accumulate (MAC) circuit;
a first permute circuit coupled between the first register file and the MAC circuit, the first permute circuit coupled to each lane of the first register output lanes and not coupled to any lane of the second register output lanes, the first permute circuit being configured to generate a first vector by selecting, as first permute output lanes, a first set from the first register output lanes;
a second permute circuit coupled between the first register file and the MAC circuit, the second permute circuit coupled to each lane of the first register output lanes and not coupled to any lane of the second register output lanes, the second permute circuit being configured to generate a second vector by selecting, as second permute output lanes, a second set from the first register output lanes;
a third permute circuit coupled between the second register file and the MAC circuit, the third permute circuit coupled to each lane of the second register output lanes and not coupled to any lane of the first register output lanes, the third permute circuit being configured to generate a third vector by selecting, as third permute output lanes, a third set from the second register output lanes;
a pre-adder circuit coupled between (i) both the first permute circuit and the second permute circuit and (ii) the MAC circuit, the pre-adder circuit being configured to process the first vector received from the first permute output lanes and the second vector received from the second permute output lanes, the pre-adder circuit having pre-adder output lanes coupled to the MAC circuit; and
a special operation circuit coupled between (i) both the second permute circuit and the third permute circuit and (ii) the MAC circuit, the special operation circuit being configured to selectively output a unity value and a respective sign-extended version of the second vector received from the second permute output lanes and the third vector received from the third permute output lanes, the special operation circuit having special operation output lanes coupled to the MAC circuit.

10. The IC of claim 9 , wherein the MAC circuit comprises:
a multiplier configured to process an output of the pre-adder circuit and an output of the special operation circuit;
at least one post-adder configured to process an output of the multiplier; and
an accumulator configured to process an output of the at least one post-adder.

11. The IC of claim 10 , wherein the at least one post-adder comprises a first post-adder coupled to a second post-adder.

12. The IC of claim 10 , further comprising:
a first multiplexer configured to select among the first permute output lanes, the second permute output lanes, and the third permute output lanes;
an upshift circuit coupled to an output of the first multiplexer; and
a second multiplexer coupled to an output of the upshift circuit and to the output of the at least one post-adder;
wherein the accumulator is further configured to process an output of the second multiplexer.

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Assignees

• Xilinx Inc

Inventors

• Ozgul Baris
• Langer Jan
• Noguera Serra Juan J
• Bilski Goran H K
• Walke Richard L

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title