Dual mode interconnect

Patent metadata

Field	Value
Publication number	US-2022015588-A1
Application number	US-202117468346-A
Country	US
Kind code	A1
Filing date	Sep 7, 2021
Priority date	Apr 3, 2018
Publication date	Jan 20, 2022
Grant date	—

Abstract

Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

First claim

What is claimed is:

1 . A system on a chip (SoC), comprising:
a first data processing engine in an array of data processing engines; a second data processing engine in the array of data processing engines; and an interconnect configured to transmit streaming data between the first and second data processing engines, wherein the interconnect comprises a plurality of streaming interconnects comprising ports that are selectively configurable into a circuit switching mode and a packet switching mode, wherein, when configured in the circuit switching mode, the streaming data routed through the ports is deterministic and the streaming data comprises a plurality of packets, each comprising a respective header, wherein the respective header comprises a stream ID assigning a corresponding packet to a logical stream, wherein a first streaming interconnect of the plurality of streaming interconnects comprises a first slave port, a second slave port, and a master port that are configured in the packet switching mode, wherein the first slave port transmits a first packet with a first value of the stream ID to the master port and the second slave port transmits a second packet with a second value of the stream ID to the master port, wherein the first and second packets are assigned to different logical streams, wherein, when configured in the packet switching mode, streaming data routed through the ports is non-deterministic.

2 . The SoC of claim 1 , wherein, when configured in the circuit switching mode, latency of the streaming data routed through the ports is independent of congestion in the interconnect, wherein, when configured in the packet switching mode, the latency of the streaming data is affected by congestion.

3 . The SoC of claim 1 , wherein a first streaming interconnect of the plurality of streaming interconnects comprises a third slave port and a second master port both configured in the circuit switching mode, wherein a first configuration register corresponding to the second master port stores a value specifying the third slave port as a source of streaming data for the second master port.

4 . The SoC of claim 3 , wherein the first streaming interconnect comprise a third master port configured in the circuit switching mode, wherein a second configuration register corresponding to the third master port stores a value specifying the third slave port as a source of streaming data for the third master port.

5 . The SoC of claim 4 , wherein the second and third master ports receive data only from the third slave port.

6 . The SoC of claim 1 , wherein the first streaming interconnect comprises an arbiter assigned to the master port, wherein the arbiter is configured to arbitrate between the first slave port and the second slave port to determine which can transmit data to the master port to prevent a collision.

7 . The SoC of claim 1 , wherein the first streaming interconnect is configured to:
identify an arbiter using a packet header of a packet received at the first or second slave port; select a master select value using the packet header to identify the master port; identify a masking value for the master port; and routing the packet to the master port using the masking value.

8 . The SoC of claim 7 , wherein the first streaming interconnect is configured to:
perform arbitration using the arbiter upon determining at least one: (i) there are multiple pending requests from slave ports to transmit data to the master port and (ii) the master port transmits a request for arbitration.

9 . The SoC of claim 1 , wherein the circuit switching mode and the packet switching mode are compatible with Advanced Extensible Interface (AXI) streaming.

10 . A method, comprising:
configuring a first slave port and a first master port in a streaming interconnect in a circuit switching mode, wherein, when configured in the circuit switching mode, first streaming data routed through the first slave port and the first master port is deterministic; configuring a second slave port and a second master port in the streaming interconnect in a packet switching mode, wherein, when configured in the packet switching mode, second streaming data routed through the second slave port and the second master port is non-deterministic; and transmitting data between a first data processing engine in an array of data processing engines in a SoC and a second data processing engine in the array of data processing engines using the streaming interconnect; identifying an arbiter using a packet header of a packet received at the second slave port; selecting a master select value using the packet header to identify the second master port; identifying a masking value for the second master port; and routing the packet to the second master port using the masking value.

11 . The method of claim 10 , wherein, when configured in the circuit switching mode, latency of the streaming data routed through the first slave and master ports is independent of congestion in the streaming interconnect, wherein, when configured in the packet switching mode, the latency of the streaming data is affected by congestion.

12 . The method of claim 10 , further comprising:
configuring a third master port in the streaming interconnect in the circuit switching mode; and transmitting the first streaming data to the first master port and the third master port in parallel.

13 . The method of claim 12 , wherein the first and third master ports receive data only from the first slave port.

14 . The method of claim 12 , wherein the second streaming data comprises a plurality of packets, each comprising a respective header, wherein the respective header comprises a stream ID assigning a corresponding packet to a logical stream.

15 . The method of claim 14 , further comprising:
configuring a third slave port in the streaming interconnect in the packet switching mode; transmitting a first packet with a first value of the stream ID from the second slave port to the second master port; and transmitting a second packet with a second value of the stream ID from the third slave port to the second master port, wherein the first and second packets are assigned to different logical streams.

16 . The method of claim 15 , further comprising:
arbitrating between the second slave port and the third slave port to determine which can transmit data to the second master port to prevent a collision.

17 . The method of claim 10 , further comprising:
reconfiguring the first slave port and the first master port into the packet switching mode; and reconfiguring the second slave port and the second master port into the circuit switching mode.

18 . A method, comprising:
configuring a first slave port and a first master port in an streaming interconnect in a circuit switching mode, wherein, when configured in the circuit switching mode, first streaming data routed through the first slave and master ports is deterministic; configuring a second slave port and a second master port in the streaming interconnect in a packet switching mode, wherein, when configured in the packet switching mode, second streaming data routed through the second slave and master ports is non-deterministic, wherein the second streaming data comprises a plurality of packets, each comprising a respective header, wherein the respective header comprises a stream ID assigning a corresponding packet to a logical stream; transmitting data between a first data processing engine in an array of data processing engines in a SoC and a

Assignees

• Xilinx Inc

Inventors

• Mccolgan Peter
• Bilski Goran Hk
• Noguera Serra Juan J
• Langer Jan
• Ozgul Baris
• Clarke David

Classifications

• E04H15/38

  expansible, e.g. extensible {in a fan type manner} · CPC title

• Y02A50/30

  Against vector-borne diseases, e.g. mosquito-borne, fly-borne, tick-borne or waterborne diseases whose impact is exacerbated by climate change · CPC title

• E04H1/1216

  Public W.C.s · CPC title

• A47K11/02 Primary

  Dry closets, e.g. incinerator closets · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title