Memory tiles in data processing engine array

Patent metadata

Field	Value
Publication number	US-11520717-B1
Application number	US-202117196669-A
Country	US
Kind code	B1
Filing date	Mar 9, 2021
Priority date	Mar 9, 2021
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.

First claim

What is claimed is:

1. An integrated circuit having a data processing engine (DPE) array including a plurality of memory tiles, wherein each memory tile comprises:
a direct memory access (DMA) engine;
a random-access memory (RAM) connected to the DMA engine; and
a stream switch coupled to the DMA engine;
wherein a DMA engine of a first memory tile is coupled to a RAM disposed in a second memory tile;
wherein the stream switch of the first memory tile is coupled to a stream switch disposed in the second memory tile; and
wherein the plurality of memory tiles are hardwired.

2. The integrated circuit of claim 1 , wherein
the DMA engine of the first memory tile is programmable to access the RAM in the first memory tile and the RAM in the second memory tile to form a composite memory formed of the first memory tile and the second memory tile.

3. The integrated circuit of claim 2 , wherein
the first memory tile and the second memory tile are adjacent.

4. The integrated circuit of claim 1 , wherein
the DMA engine of the first memory tile is programmable to access a RAM located in a third memory tile.

5. The integrated circuit of claim 4 , wherein
the third memory tile is adjacent to the first memory tile.

6. The integrated circuit of claim 1 , wherein
the first memory tile includes first event broadcast circuitry configured to generate events corresponding to read and write operations of the DMA engine disposed in the first memory tile; and
the first event broadcast circuitry is programmable to provide selected ones of the events to one or more selected destination circuits.

7. The integrated circuit of claim 6 , wherein
the first event broadcast circuitry is connected to second event broadcast circuitry of the second memory tile.

8. The integrated circuit of claim 6 , wherein
the first memory tile includes a control, debug, and trace circuit configured to packetize the selected events and provide the packetized selected events to the stream switch of the first memory tile; and
the stream switch of the first memory tile is configured to send the packetized selected events to a further destination circuit.

9. The integrated circuit of claim 1 , wherein
the first memory tile includes a first lock circuit coupled to the DMA engine of the first memory tile and to a DMA engine of the second memory tile; and
the lock circuit is configured to grant requests for locks for portions of the RAM of the first memory tile received from the DMA engine of the first memory tile and the DMA engine of the second memory tile.

10. The integrated circuit of claim 1 , wherein
the first memory tile includes a memory mapped switch configured to receive configuration data to program the stream switch of the first memory tile and the DMA engine of the first memory tile.

11. The integrated circuit of claim 10 , wherein
the DPE array includes a plurality of tiles arranged in a grid having columns and rows;
the memory mapped switch of the first memory tile is connected to a memory mapped switch in an above adjacent tile and a memory mapped switch in a below adjacent tile; and
the memory mapped switches are configured to convey configuration data among the tiles of the DPE array in a same column.

12. The integrated circuit of claim 1 , wherein each RAM of a memory tile includes:
a plurality of arbitration circuits; and
a plurality of memory banks coupled to respective ones of the plurality of arbitration circuits; and
wherein an arbitration circuit of the first memory tile is coupled to a plurality of stream-to-memory mapped channels of the DMA engine of the first memory tile, a plurality of memory mapped-to-stream channels of the DMA engine of the first memory tile, and to a plurality of arbitration circuits coupled to respective memory banks of the RAM of the second memory tile.

13. The integrated circuit of claim 12 , wherein
the first memory tile includes a memory mapped switch configured to receive configuration data to program the stream switch of the first memory tile and the DMA engine of the first memory tile; and
the memory mapped switch of the first memory tile is coupled to each arbitration circuit of the plurality of arbitration circuits of the first memory tile.

14. The integrated circuit of claim 1 , wherein
the DMA engine of each memory tile includes a plurality of stream-to-memory mapped channels, wherein each stream-to-memory mapped channel is independently configurable to operate using one of a plurality of different packet processing modes.

15. The integrated circuit of claim 14 , wherein
the plurality of packet processing modes include:
an in-order mode where packets received from other tiles of the DPE array arrive in a predetermined order; and
an out-of-order mode where packets received from other tiles of the DPE array arrive in a non-deterministic order.

16. The integrated circuit of claim 1 , wherein
the DMA engine of each memory tile includes a plurality of stream-to-memory mapped channels, wherein at least one of the plurality of stream-to-memory mapped channels is configured to operate using an out-of-order mode where packets received from other tiles of the DPE array arrive in a non-deterministic order.

17. The integrated circuit of claim 1 , wherein the DPE array comprises:
a plurality of tiles arranged in a grid having rows and columns, wherein the plurality of tiles include a plurality of DPE tiles, the plurality of memory tiles, and a plurality of interface tiles;
wherein the plurality of interface tiles form an SoC interface that communicatively links the DPE array with one or more other circuit blocks of the integrated circuit.

18. The integrated circuit of claim 17 , wherein
each DPE tile includes a DMA engine including a plurality of stream-to-memory mapped channels, wherein each stream-to-memory mapped channel is independently configurable to operate using one of a plurality of different packet processing modes.

19. The integrated circuit of claim 18 , wherein
the plurality of packet processing modes include:
an in-order mode where packets received from other tiles of the DPE array arrive in a predetermined order; and
an out-of-order mode where packets received from other tiles of the DPE array arrive in a non-deterministic order.

20. The integrated circuit of claim 17 , wherein
each DPE tile includes a DMA engine including a plurality of stream-to-memory mapped channels, wherein at least one of the plurality of stream-to-memory mapped channel is configured to operate using an out-of-order mode where packets received from other tiles of the DPE array arrive in a non-deterministic order.

Assignees

• Xilinx Inc

Inventors

• Clarke David
• Mccolgan Peter
• Dickman Zachary
• Marques Jose
• Serra Juan J Noguera
• Tuan Tim
• Ozgul Baris
• Langer Jan

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title