Method for sharing a storage device among multiple processors and associated electronic device
US-2024211415-A1 · Jun 27, 2024 · US
Physics
Physics · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F13/1663 |
| Official title | — |
| Display label | Physics (mapped technology topic) |
| Total patents | 1,379 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 96 |
| 2016 | 141 |
| 2017 | 123 |
| 2018 | 118 |
| 2019 | 156 |
| 2020 | 137 |
| 2021 | 114 |
| 2022 | 120 |
| 2023 | 113 |
| 2024 | 110 |
| 2025 | 122 |
| 2026 | 29 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES
US-2024152297-A1 · May 9, 2024 · US
Memory mechanism for providing semaphore functionality in multi-master processing environment
US-2015378939-A1 · Dec 31, 2015 · US
Collecting transactional execution characteristics during transactional execution
US-2015378779-A1 · Dec 31, 2015 · US
Memory transaction having implicit ordering effects
US-2015370500-A1 · Dec 24, 2015 · US
Information processing apparatus, input and output control device, and method of controlling information processing apparatus
US-2015370732-A1 · Dec 24, 2015 · US
Reader-writer synchronization with high-performance readers and low-latency writers
US-9218305-B2 · Dec 22, 2015 · US
Memory sharing circuit employing a buffered address and data bus and preventing bus collision
US-9218306-B2 · Dec 22, 2015 · US
Reader-writer synchronization with high-performance readers and low-latency writers
US-9218307-B2 · Dec 22, 2015 · US
Pulse-latch based bus design for increased bandwidth
US-2015363352-A1 · Dec 17, 2015 · US
High-speed memory system
US-2015356044-A1 · Dec 10, 2015 · US
Raw memory transaction support
US-9208110-B2 · Dec 8, 2015 · US
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
US-9208120-B2 · Dec 8, 2015 · US
Hierarchical in-memory sort engine
US-2015347592-A1 · Dec 3, 2015 · US
Power management for a computer system
US-9201490-B2 · Dec 1, 2015 · US
Multi-port memory that supports multiple simultaneous write operations
US-9195622-B1 · Nov 24, 2015 · US
Transaction info bypass for nodes coupled to an interconnect fabric
US-9195610-B2 · Nov 24, 2015 · US
Programmable address-based write-through cache control
US-9189331-B2 · Nov 17, 2015 · US
Computer architecture having selectable, parallel and serial communication channels between processors and memory
US-2015317277-A1 · Nov 5, 2015 · US
Recursive use of multiple hardware lookup structures in a transactional memory
US-9176905-B1 · Nov 3, 2015 · US
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F13/1663?
- CPC G06F13/1663 is the Cooperative Patent Classification code for “Physics.”
- How many patents are filed under CPC G06F13/1663 (Physics)?
- Our database includes 1,379 publications tagged with this CPC code.
- Is patent activity under CPC G06F13/1663 growing?
- Publication counts under this code: 110 in 2024 vs 122 in 2025 (latest complete years).