System-on-chip interface architecture

Patent metadata

Field	Value
Publication number	US-10635622-B2
Application number	US-201815944617-A
Country	US
Kind code	B2
Filing date	Apr 3, 2018
Priority date	Apr 3, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.

First claim

What is claimed is:

1. A device, comprising:
a plurality of data processing engines;
a subsystem;
a System-on-Chip (SoC) interface block coupled to the plurality of data processing engines and the subsystem, wherein the SoC interface block is configured to exchange data between the subsystem and the plurality of data processing engines;
wherein the SoC interface block includes a plurality of tiles, where each tile is configured to communicate with a subset of the plurality of data processing engines; and
wherein each tile comprises a memory mapped switch configured to provide a first portion of configuration data to at least one neighboring tile and to provide a second portion of the configuration data to at least one of the subset of the plurality of data processing engines.

2. The device of claim 1 , wherein the subsystem includes programmable logic.

3. The device of claim 1 , wherein the subsystem includes a processor configured to execute program code.

4. The device of claim 1 , wherein the subsystem includes at least one of an application-specific integrated circuit or analog/mixed signal circuitry.

5. The device of claim 1 , wherein each tile comprises:
a stream switch configured to provide first data to at least one neighboring tile and to provide second data to at least one of the plurality of data processing engines.

6. The device of claim 1 , wherein each tile comprises:
event broadcast circuitry configured to receive events generated within the tile and events from circuitry external to the tile, wherein the event broadcast circuitry is programmable to provide selected ones of the events to selected destinations.

7. The device of claim 6 , wherein the SoC interface block further comprises:
a control, debug, and trace circuit configured to packetize the selected events and provide the packetized selected events to the subsystem.

8. The device of claim 6 , wherein the SoC interface block further comprises:
an interface that couples the event broadcast circuitry to the subsystem.

Assignees

• Xilinx Inc

Inventors

• Bilski Goran H K
• Noguera Serra Juan J
• Clarke David
• Tuan Tim
• Mccolgan Peter
• Dickman Zachary
• Ozgul Baris
• Langer Jan

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/1684

  using multiple buses · CPC title

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06F15/7807 Primary

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F2213/0038

  System on Chip · CPC title