Device with data processing engine array that enables partial reconfiguration

Patent metadata

Field	Value
Publication number	US-12105667-B2
Application number	US-202318114850-A
Country	US
Kind code	B2
Filing date	Feb 27, 2023
Priority date	Apr 3, 2018
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

First claim

What is claimed is:

1. A method comprising:
operating a first kernel loaded on a first subset of data processing engines (DPEs) and a second kernel loaded on a second subset of the DPEs, each DPE of the DPEs comprising a core and a configuration memory space;
generating an indication of a conclusion of a task associated with the second kernel;
loading configuration data of a third kernel on a third subset of the DPEs based on the conclusion of the task associated with the second kernel; and
operating the first kernel loaded on the first subset of the DPEs and the third kernel on the third subset of the DPEs.

2. The method of claim 1 , wherein the configuration data of the third kernel is loaded on the third subset of the DPEs without modifying operation of the first kernel on the first subset of the DPEs.

3. The method of claim 1 , wherein the second subset of the DPEs and the third subset of the DPEs have at least one DPE of the DPEs in common.

4. The method of claim 1 , wherein the first subset of the DPEs and the second subset of the DPEs differ in at least one of hardware resources, data, and control dependency, and wherein a data flow associated with the first kernel is independent from the data flow associated with the second kernel.

5. The method of claim 1 , wherein operation of the first kernel at least partially overlaps with loading the configuration data of the third kernel on the third subset of the DPEs.

6. The method of claim 1 , wherein the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs have a shared hardware resource, and wherein a data flow associated with the third kernel flows through at least one DPE of the first subset of the DPEs.

7. The method of claim 6 , wherein operation of the first kernel is stalled during a period that at least partially overlaps with loading the configuration data of the third kernel on the third subset of the DPEs.

8. The method of claim 6 , wherein a data and/or control dependency exists between the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs.

9. The method of claim 1 further comprising loading configuration data for a hardware resource in at least one of the DPEs of the first subset of the DPEs, wherein the hardware resource is shared between the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs.

10. The method of claim 1 , wherein a data path associated with the second kernel includes a first DPE of the first subset of the DPEs, and a data path associated with the third kernel includes a second DPE of the first subset of the DPEs, the first DPE differs from the second DPE.

11. The method of claim 1 , wherein each DPE of the DPEs includes a stream switch configured to communicate application data with a neighboring DPE of the DPEs.

12. A device comprising:
data processing engines (DPEs), each DPE of the DPEs comprising a core and program memory, wherein:
a first subset of the DPEs is configured to operate a first kernel loaded on the first subset;
a second subset of the DPEs is configured to operate a second kernel loaded on the second subset; and
a third subset of the DPEs is configured to operate a third kernel, and wherein configuration data associated with the third kernel is loaded on the third subset based on a determination that a task associated with the second kernel has concluded.

13. The device of claim 12 , wherein:
the second subset of the DPEs and the third subset of the DPEs have at least one DPE of the DPEs in common; or
the second subset of the DPEs and the third subset of the DPEs are non-overlapping, and wherein a data path associated with the third kernel includes at least one DPE of the second subset of the DPEs.

14. The device of claim 12 , wherein:
operation of the first kernel at least partially overlaps with loading the configuration data of the third kernel on the third subset of the DPEs; and
the first subset of the DPEs and the second subset of the DPEs differ in at least one of hardware resources, data, and control dependency, and wherein a data flow associated with the first kernel is independent from the data flow associated with the second kernel.

15. The device of claim 12 , wherein:
the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs have a shared hardware resource, and wherein a data flow associated with the third kernel flows through at least one DPE of the first subset of the DPEs; and
operation of the first kernel is stalled during a period that at least partially overlaps with loading the configuration data of the third kernel on the third subset of the DPEs.

16. The device of claim 12 , wherein a data and/or control dependency exists between the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs, and wherein the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs have a shared hardware resource.

17. The device of claim 12 , wherein loading the configuration data on the third subset of the DPEs includes loading configuration data for a hardware resource in at least one of the DPEs of the first subset of the DPEs, wherein the hardware resource is shared between the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs.

18. A device comprising:
data processing engines (DPEs), each DPE of the DPEs comprising a core, a configuration memory space, and a stream switch configured to communicate application data to a neighboring DPE of the DPEs, wherein:
each DPE of the DPEs is independently configurable; and
the DPEs are configured to:
operate a first kernel on a first subset of the DPEs; and

reconfigure a third subset of the DPEs to operate a third kernel based on determining that a task associated with a second kernel operating on a second subset of the DPEs has concluded.

19. The device of claim 18 , wherein:
operation of the first kernel at least partially overlaps with loading configuration data of the third kernel on the third subset of the DPEs; and
the first subset of the DPEs and the second subset of the DPEs differs in at least one of hardware resources, data, and control dependency, and wherein a data flow associated with the first kernel is independent from the data flow associated with the second kernel.

20. The device of claim 18 , wherein:
the first kernel operating on the first subset of the DPEs and the third kernel operating on the third subset of the DPEs have a shared hardware resource, and wherein a data flow associated with the third kernel flows through the stream switch of a first DPE of the first subset of the DPEs; and
operation of the first kernel is stalled during a period that at least partially overlaps with loading the configuration data of the third kernel on the third subset of the DPEs.

Assignees

• Xilinx Inc

Inventors

• Noguera Serra Juan J
• Date Sneha Bhalchandra
• Langer Jan
• Ozgul Baris
• Bilski Goran H K

Classifications

• G06F1/24

  Resetting means · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/17306

  Intercommunication techniques · CPC title