Data processing engine arrangement in a device

Patent metadata

Field	Value
Publication number	US-10866753-B2
Application number	US-201815944160-A
Country	US
Kind code	B2
Filing date	Apr 3, 2018
Priority date	Apr 3, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

First claim

What is claimed is:

1. A device, comprising:
a plurality of data processing engines;
wherein each data processing engine includes a core and a memory module;
wherein the plurality of data processing engines are organized in a plurality of rows, and wherein the cores and the memory modules within each respective row of the plurality of rows are aligned in a direction parallel to the row;
wherein each core is configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines; and
wherein the cores of the plurality of data processing engines lack input interrupts to provide deterministic and uninterrupted operation.

2. The device of claim 1 , wherein the memory module of each data processing engine includes a random access memory and a plurality of memory interfaces to the random access memory, wherein a first of the plurality of memory interfaces is directly connected to the core within the same data processing engine and each other one of the plurality of memory interfaces is directly connected to a core of a different one of the plurality of data processing engines.

3. The device of claim 2 , wherein the plurality of data processing engines are further organized in a plurality of columns, wherein the plurality of columns are perpendicular to the plurality of rows, and wherein the cores of the plurality of data processing engines in the columns are aligned and the memory modules of the plurality of data processing engines in the columns are aligned.

4. The device of claim 3 , wherein a memory module of a selected data processing engine of the plurality of data processing engines includes:
a first memory interface coupled to a core of a data processing engine of the plurality of data processing engines immediately above the selected data processing engine;
a second memory interface coupled to a core within the selected data processing engine;
a third memory interface coupled to a core of a data processing engine of the plurality of data processing engines immediately adjacent the selected data processing engine; and
a fourth memory interface coupled to a core of a data processing engine of the plurality of data processing engines immediately below the selected data processing engine.

5. The device of claim 3 , wherein a selected data processing engine of the plurality of data processing engines is configured to communicate, via shared access to memory modules, with a group of at least ten of the plurality of data processing engines.

6. The device of claim 5 , wherein at least two data processing engines of the group are configured to access more than one memory module of the group of at least ten of the plurality of data processing engines.

7. The device of claim 1 , wherein the plurality of rows of data processing engines comprise:
a first row having a first subset of the plurality of data processing engines, wherein each data processing engine of the first subset has the memory module located on a first side of the core; and
a second row having a second subset of the plurality of data processing engines, wherein each data processing engine of the second subset has the memory module located on a second side of the core, wherein the first side and the second side are opposing.

8. The device of claim 7 , wherein a memory module of a first selected data processing engine of the plurality of data processing engines of the first row and a second selected data processing engine of the plurality of data processing engines of the second row each include:
a first memory interface coupled to a core of a data processing engine of the plurality of data processing engines immediately above the selected data processing engine;
a second memory interface coupled to a core within the selected data processing engine;
a third memory interface coupled to a core of a data processing engine of the plurality of data processing engines immediately adjacent the selected data processing engine; and
a fourth memory interface coupled to a core of a data processing engine of the plurality of data processing engines immediately below the selected data processing engine.

9. The device of claim 7 , wherein a selected data processing engine of the plurality of data processing engines is configured to communicate, via shared access to memory modules, with a group of at least eight of the plurality of data processing engines.

10. The device of claim 9 , wherein at least four data processing engines of the group are configured to access more than one memory module of the group of at least eight of the plurality of data processing engines.

Assignees

• Xilinx Inc

Inventors

• Noguera Serra Juan J
• Bilski Goran H K
• Langer Jan
• Ozgul Baris
• Tuan Tim
• Walke Richard L
• Wittig Ralph D
• Vissers Kornelis A
• Clarke David

Classifications

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F15/17337 Primary

  Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004) · CPC title

• G06F13/1663

  Access to shared memory · CPC title

• G06F15/7807 Primary

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F15/17331 Primary

  Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title