Apparatuses systems and methods for linked bank refresh
US-2026038562-A1 · Feb 5, 2026 · US
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Howe Gary patents
Howe Gary is listed as an inventor on 38 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Howe Gary |
| Total patents | 38 |
| First publication | Feb 17, 2015 |
| Latest publication | Feb 5, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatuses and methods for multiple power down and exit modes in memory devices
US-2026037053-A1 · Feb 5, 2026 · US
Setting termination impedance based on encoding bits in a command
US-2026037133-A1 · Feb 5, 2026 · US
Apparatuses and methods for memory array with activate based count access count update and background refresh
US-2026038557-A1 · Feb 5, 2026 · US
Apparatuses systems and methods for memory with access based refresh control
US-2025299722-A1 · Sep 25, 2025 · US
Apparatuses systems and methods for memory with access based refresh control
US-2025299723-A1 · Sep 25, 2025 · US
Apparatuses systems and methods for memory with access based refresh control
US-2025299719-A1 · Sep 25, 2025 · US
Apparatuses systems and methods for memory with access based refresh control
US-2025299720-A1 · Sep 25, 2025 · US
Apparatuses systems and methods for memory with access based refresh control
US-2025299721-A1 · Sep 25, 2025 · US
Apparatuses and methods for bad row mode
US-11915775-B2 · Feb 27, 2024 · US
Recent patents
Latest publications not already listed above.
Command address input buffer bias current reduction
US-2023401008-A1 · Dec 14, 2023 · US
Apparatuses and methods for refresh address masking
US-11670356-B2 · Jun 6, 2023 · US
Configurable soft post-package repair (SPPR) schemes
US-11646095-B2 · May 9, 2023 · US
Apparatuses and methods for bad row mode
US-2023096291-A1 · Mar 30, 2023 · US
Apparatuses and methods for refresh address masking
US-2023020753-A1 · Jan 19, 2023 · US
Methods for on-die memory termination and memory devices and systems employing the same
US-11545199-B2 · Jan 3, 2023 · US
Configurable Soft Post-Package Repair (SPPR) Schemes
US-2021280267-A1 · Sep 9, 2021 · US
Command address input buffer bias current reduction
US-11099774-B2 · Aug 24, 2021 · US
Methods for on-die memory termination and memory devices and systems employing the same
US-2021201970-A1 · Jul 1, 2021 · US
Methods for on-die memory termination and memory devices and systems employing the same
US-10950282-B2 · Mar 16, 2021 · US
Devices and methods to write background data patterns in memory devices
US-10672496-B2 · Jun 2, 2020 · US
Write level initialization synchronization
US-10664173-B2 · May 26, 2020 · US
Methods for on-die memory termination and memory devices and systems employing the same
US-2019371379-A1 · Dec 5, 2019 · US
Methods for on-die memory termination and memory devices and systems employing the same
US-10424356-B2 · Sep 24, 2019 · US
Write level initialization syncronization
US-2019235760-A1 · Aug 1, 2019 · US
Apparatuses and methods for timing domain crossing
US-10318238-B2 · Jun 11, 2019 · US
Methods for on-die memory termination and memory devices and systems employing the same
US-2019156871-A1 · May 23, 2019 · US
Devices and Methods to Write Background Data Patterns in Memory Devices
US-2019122744-A1 · Apr 25, 2019 · US
Command address input buffer bias current reduction
US-2019065106-A1 · Feb 28, 2019 · US
Apparatuses and methods for timing domain crossing
US-2018357041-A1 · Dec 13, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 37 |
| Vankayala Vijayakrishna J | 1 |
| Howe Gary | 1 |
| Winegard John | 1 |
| Surlekar Vipul | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C7/1084 | 11 |
| G06F3/0673 | 11 |
| G11C7/1045 | 10 |
| G11C7/22 | 10 |
| G11C11/4087 | 9 |