Write level initialization synchronization

Patent metadata

Field	Value
Publication number	US-10664173-B2
Application number	US-201815883956-A
Country	US
Kind code	B2
Filing date	Jan 30, 2018
Priority date	Jan 30, 2018
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.

First claim

What is claimed is:

1. A memory system, comprising:
a controller configured to send read commands, write commands, or read and write commands to a memory device;
the memory device, configured to implement the read commands, write commands, or read and write commands;
timing skew compensation logic, comprising circuitry configured to compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK) by:
executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between the DQS and the CLK;
identifying the internal and external timing skew based upon the WLInit; and
adjusting a timing between the DQS and the CLK based upon the internal and external timing skew, the internal timing skew comprising skew caused internal to the memory device and the external timing skew comprising skew caused external to the memory device.

2. The memory system of claim 1 , wherein the timing skew compensation logic comprises circuitry configured to compensate for the internal and external timing skew by causing performance of multiple passes of the write leveling initialization procedure (WLInit) that uses the mode-register-write (MRW) command to synchronize a timing between the DQS with the CLK using an internal write command.

3. The memory system of claim 2 , wherein the timing skew compensation logic comprises circuitry configured to:
determine, at the memory device, whether an internal write command of the WLInit is captured in a capture window defined by the internal timing skew;
when the internal write command is not captured in the capture window, generate an initialization failure indication and provide the failure indication to the controller to trigger adjustment of the timing between the DQS and the CLK by the controller and to initiate a subsequent WLInit; and
when the internal write command is captured in the capture window, generate an initialization success indication and provide the initialization success indication to the controller to end the WLInit.

4. The memory system of claim 3 , wherein the timing skew compensation logic comprises circuitry configured to:
when the internal write command is captured in the capture window, adjust, at the memory device, the timing between the DQS and the CLK by a number of clock cycles, such that a target capture edge of the DQS is synchronized with the capture window.

5. The memory system of claim 2 , wherein the timing skew compensation logic comprises circuitry configured to:
determine, at the memory device, whether an internal write command of the WLInit is captured in a capture window defined by the internal timing skew;
when the internal write command is not captured in the capture window:
shift launch of the internal write command to attempt to capture the internal write command in the capture window;
when the internal write command is subsequently successfully captured in the capture window, generate an initialization success indication and provide the initialization success indication to the controller; and
when the internal write command is not subsequently successfully captured in the capture window, generate an initialization failure indication and provide the initialization failure indication to the controller to trigger a subsequent WLInit by the controller.

6. The memory system of claim 5 , wherein the timing skew compensation logic comprises circuitry configured to:
when the internal write command is captured in the capture window, adjust, at the memory device, the timing between the DQS and the CLK by a number of clock cycles, such that a target capture edge of the DQS is synchronized with the capture window.

7. The memory system of claim 1 , wherein the timing skew compensation logic comprises circuitry configured to compensate for the internal and external timing skew by causing performance of a single pass of the write level initialization procedure (WLInit) that uses the mode-register-write (MRW) command to synchronize the DQS with the CLK using an internal write command.

8. The memory system of claim 7 , wherein timing skew compensation logic comprises circuitry configured to:
launch, at the memory device, multiple write pulses in response to the MRW command provided from the controller;
identify, at the memory device, capture states of the multiple write pulses;
determine, at the memory device, a compensation shift based upon the capture states; and
perform the compensation shift.

9. The memory system of claim 8 , where the compensation shift is performed by the memory device.

10. The memory system of claim 8 , where the compensation shift is performed by the controller.

11. The memory system of claim 7 , wherein timing skew compensation logic comprises circuitry configured to:
extend the DQS by adding additional pulses until the internal write command is successfully captured;
extend the internal write command until the internal write command is successfully captured;
count a number of strobes of the DQS away from successful capture of the internal write command; and
provide the number of strobes to the controller, such that the controller can implement a timing adjustment between the DQS and the CLK based upon the number of strobes.

12. The memory system of claim 11 , wherein the timing skew compensation logic comprises circuitry configured to:
identify whether a first edge of the DQS captures the internal write command; and
when the first edge of the DQS captures the internal write command, return an error code rather than the number of strobes to the controller.

13. The memory system of claim 11 , wherein the timing skew compensation logic comprises circuitry configured to:
identify whether a pulse count of the DQS is greater than a predetermined threshold; and
when the pulse count of the DQS is greater than the predetermined threshold, return an error code rather than the number of strobes to the controller.

14. A tangible, non-transitory, machine-readable medium, comprising machine readable instructions that, when executed by one or more processors, cause the processors to:
compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by:
executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between the data strobe (DQS) and the clock (CLK) based upon capture of an internal write command;
identifying the internal and external timing skew based upon the WLInit; and
adjusting a timing between the DQS and the CLK based upon the internal and external timing skew;

wherein the internal timing skew comprises skew caused internal to a memory device and the external timing skew comprises skew caused external to the memory device.

15. The machine-readable medium of claim 14 , comprising machine-readable instructions that, when executed by the one or more processors, cause the processors to:
adjust the timing between the DQS and the CLK and execute a second WLInit when the internal write command is not captured.

16. The machine-readable medium of claim 14 , comprising machine-readable instructions that, when executed by the one or more processors, cause the processors to:
determine whether the internal write command is captured;
when the internal write command is not captured:
shift launch of the internal write command to attempt to capture the internal write command;
when the internal write command is subsequently successfully captured, generate an initiali

Assignees

• Micron Technology Inc

Inventors

• Howe Gary
• Chen Liang
• Penney Daniel B

Classifications

• G06F3/0673

  Single storage device · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C29/50012

  of timing · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title