Methods for on-die memory termination and memory devices and systems employing the same

Patent metadata

Field	Value
Publication number	US-11545199-B2
Application number	US-202117200233-A
Country	US
Kind code	B2
Filing date	Mar 12, 2021
Priority date	Nov 22, 2017
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

First claim

What is claimed is:

1. A method of operating a memory system, comprising:
receiving a first command instructing a memory device of the memory system to enter an on-die termination mode;
in response to the first command, placing the memory device in the on-die termination mode;
receiving a second command instructing the memory device to perform a data communication; and
in response to the second command:
exiting the memory device from the on-die termination mode,
performing, with the memory device, the data communication, and
reverting the memory device to the on-die termination mode after performing the data communication.

2. The method of claim 1 , wherein the first command includes a number of bursts or clock cycles for which a second memory device is to remain in or to continue reverting to the on-die termination mode.

3. The method of claim 1 , wherein the memory device is configured to remain in or to continue reverting to the on-die termination mode until receiving a third command instructing the memory device to exit the on-die termination mode.

4. The method of claim 1 , further comprising:
receiving a third command instructing the memory device to exit the on-die termination mode; and
in response to the third command, exiting the memory device from the on-die termination mode.

5. The method of claim 1 , further comprising:
receiving a third command instructing the memory device to perform a second data communication; and
in response to the third command:
exiting the memory device from the on-die termination mode,
performing, with the memory device, the second data communication, and
reverting the memory device to the on-die termination mode after performing the second data communication.

6. The method of claim 1 , wherein the data communication is one of a read or a write operation.

7. The method of claim 1 , wherein the memory device is a dynamic random access memory (DRAM) device.

8. The method of claim 1 , wherein the memory device corresponds to a channel of the memory system.

9. A memory device, comprising:
circuitry configured to implement an on-die termination mode at a portion of the memory device,
wherein the circuitry is further configured, in response to a single command to the portion, to:
exit the on-die termination mode at the portion during a data communication of the portion, and
revert to the on-die termination mode at the portion after the data communication.

10. The memory device of claim 9 , wherein the circuitry is configured to implement the on-die termination mode at the portion in response to a first command to implement the on-die termination mode, and to remain in or to continue reverting to the on-die termination mode until receiving a second command to exit the on-die termination mode.

11. The memory device of claim 9 , wherein the circuitry is configured to implement the on-die termination mode at the portion until a threshold number of data communications are performed by the memory device, wherein the threshold number is indicated in a first command to the portion to implement the on-die termination mode at the portion.

12. The memory device of claim 9 , wherein the memory device is dynamic random access memory (DRAM) device.

13. The memory device of claim 9 , wherein the portion corresponds to a channel of the memory device.

14. A memory system, comprising:
a first memory device; and
a second memory device configured to:
receive a first command instructing the second memory device to enter an on-die termination mode;
place, in response to the first command, the second memory device in the on-die termination mode during a first data communication of the first memory device;
receive a second command instructing the second memory device to perform a second data communication; and
in response to the second command:
exiting the second memory device from the on-die termination mode,
performing, with the second memory device, the second data communication, and
reverting the second memory device to the on-die termination mode after performing the second data communication.

15. The memory system of claim 14 , wherein the second memory device is further configured to remain in the on-die termination mode in response to the first command for a duration greater than that of the first data communication of the first memory device.

16. The memory system of claim 14 , wherein the first command includes a number of bursts or clock cycles for which the second memory device is to remain in or to continue reverting to the on-die termination mode.

17. The memory system of claim 14 , wherein the second memory device is configured to remain in or to continue reverting to the on-die termination mode until receiving a third command instructing the memory device to exit the on-die termination mode.

18. The memory system of claim 14 , wherein the data communication is one of a read or a write operation.

19. The memory system of claim 14 , wherein the first and second memory devices are dynamic random access memory (DRAM) devices.

20. The memory system of claim 14 , wherein the first and second memory devices correspond to first and second channels of the memory system, respectively.

Assignees

• Micron Technology Inc

Inventors

• Howe Gary
• Stave Eric J
• Kinsley Thomas H
• Prather Matthew A

Classifications

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C2207/10

  Aspects relating to interfaces of memory device to external buses · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title