Command address input buffer bias current reduction

Patent metadata

Field	Value
Publication number	US-11099774-B2
Application number	US-201715691447-A
Country	US
Kind code	B2
Filing date	Aug 30, 2017
Priority date	Aug 30, 2017
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.

First claim

What is claimed is:

1. A memory device comprising:
one or more memory banks configured to store data; and
one or more input buffers configured to receive command address signals to access the one or more memory banks;
wherein the memory device is configured to operate in each of a first mode of operation and a second mode of operation; and
wherein the one or more input buffers are configured to operate under a first bias current when the memory device is in the first mode of operation and configured to operate under a second bias current when the memory device is in the second mode of operation, and wherein the first bias current is greater than the second bias current, wherein the memory device is configured to operate in conjunction with a clock signal, wherein the clock signal has a clock frequency, and wherein the clock frequency is faster in the second mode of operation than in the first mode of operation.

2. The memory device of claim 1 , wherein the memory device is a dynamic random-access memory device.

3. The memory device of claim 2 , wherein the dynamic random-access memory device is a double data rate type five synchronous dynamic random access memory device.

4. The memory device of claim 1 , wherein the first mode of operation is a 1N mode, and the second mode of operation is a 2N mode.

5. The memory device of claim 1 , wherein the first bias current is approximately 500 microamps (μA).

6. The memory device of claim 1 , wherein the second bias current is approximately 50% of the first bias current.

7. The memory device of claim 1 , comprising a command decoder configured to receive the command address signals from the one or more input buffers and wherein the command decoder is configured to decode the command address signals.

8. The memory device of claim 1 , wherein the command address signals comprise a two-cycle command.

9. The memory device of claim 1 , wherein the memory device is configured to be implemented in a system with a motherboard and a processor.

10. The memory device of claim 1 , wherein the one or more input buffers are configured to receive a 2N signal, that when asserted, causes the one or more input buffers to switch from the first bias current to the second bias current.

11. The memory device of claim 1 , wherein the command address signals are temporarily stored in the one or more input buffers.

12. A memory device comprising:
one or more memory banks configured to store data; and
a command address input circuit configured to receive command address signals to access the one or more memory banks, wherein the command address input circuit comprises one or more input buffers configured to receive the command address signals, a voltage reference signal, and a mode signal,
wherein the one or more input buffers are configured to compare the command address signals to the voltage reference signal to determine a state of the command address signals,
wherein the one or more input buffers are configured to operate at a first current when the mode signal is not asserted, and the one or more input buffers are configured to operate at a second current when the mode signal is asserted, wherein the first current is greater than the second current,
wherein, when the mode signal is asserted, the one or more input buffers are configured to skip one or more clock cycles while receiving the command address signals or comparing the command address signals.

13. The memory device of claim 12 , wherein command address input circuit comprises a command address voltage reference generator, wherein the command address voltage reference generator is configured to provide the voltage reference signal to the one or more input buffers.

14. The memory device of claim 12 , wherein the command address input circuit comprises one or more latches configured to receive the state of the command address signals from the one or more input buffers.

15. The memory device of claim 14 , wherein the latches are configured to utilize a clock signal to regulate a transmission of the state of the command address signals.

16. The memory device of claim 12 , wherein the mode signal is asserted upon initialization of the memory device.

17. The memory device of claim 12 , wherein the mode signal is asserted based upon a selection by a user of the memory device.

18. The memory device of claim 12 , wherein the second bias current of the second mode of operation is automatically adjusted based on at least a clock signal.

19. A method comprising:
receiving, at a memory device, a mode signal;
engaging, at the memory device, one of a first mode of operation or a second mode of operation based at least on the mode signal;
decreasing a bias current of an input buffer of the memory device when the second mode of operation is engaged; and
in response to the second mode of operation being engaged, skipping one or more clock cycles while receiving the command address signals or comparing the command address signals.

20. The method of claim 19 , wherein the mode signal is provided to the memory device by an external device.

21. The method of claim 19 , comprising monitoring, at the memory device, a clock frequency, a command address loading, or both to determine an optimal mode between the first mode of operation and the second mode of operation.

22. The method of claim 21 , comprising asserting, within the memory device, the mode signal to the input buffer, wherein the mode signal decreases the bias current of the input buffer.

23. The method of claim 19 , wherein the bias current, when in the second mode of operation, is between 20% and 80% of the bias current when in the first mode of operation.

Assignees

• Micron Technology Inc

Inventors

• Howe Gary

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G06F13/161

  with latency improvement · CPC title

• G11C11/407

  for memory cells of the field-effect type · CPC title

• E21B10/5735

  Interface between the substrate and the cutting element · CPC title