Apparatuses and methods for refresh address masking

Patent metadata

Field	Value
Publication number	US-11670356-B2
Application number	US-202117305878-A
Country	US
Kind code	B2
Filing date	Jul 16, 2021
Priority date	Jul 16, 2021
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

First claim

What is claimed is:

1. An apparatus comprising:
a fuse latch configured to store a selected address;
a refresh address generator configured to generate a refresh address as part of an application operation, wherein the refresh address is associated with a plurality of word lines;
a section decoder configured to generate a section enable signal based on the refresh address;
a comparator configured to provide a refresh stop signal at an active level if the selected address matches the refresh address;
a logic circuit configured to pass the section enable signal if the refresh stop signal is inactive and configured to suppress the section enable signal if the refresh stop signal is active; and
a row decoder configured to refresh a word line associated with the refresh address if the refresh stop signal is inactive and configured to not refresh the word line if the refresh stop signal is active, wherein all of the plurality of word lines are not refreshed if the refresh stop signal is active.

2. An apparatus, comprising:
a fuse latch configured to store a selected address;
a refresh address generator configured to generate a refresh address as part of an application operation, wherein the refresh address is associated with a plurality of word lines and wherein the selected address is associated with one of the plurality of word lines;
a comparator configured to provide a refresh stop signal at an active level if the selected address matches the refresh address;
a row decoder configured to refresh a word line associated with the refresh address if the refresh stop signal is inactive and configured to not refresh the word line if the refresh stop signal is active, wherein the one of the plurality of word lines is not refreshed and a remainder of the plurality of word lines are refreshed when the refresh stop signal is active;
a first decoder configured to generate a section enable signal based on the refresh address, wherein the section enable signal has a number of bits, each associated with a word line; and
a second decoder configured to generate a section mask signal based on the selected address, wherein the section mask signal has a number of bits corresponding to the number of bits of the section enable signal, and wherein one of the section mask bits is active based on the selected address, and wherein one of the number of bits of the section enable signal associated with the active bit of the section mask signal is suppressed.

3. The apparatus of claim 1 , wherein the selected address is associated with a defective word line of a memory array.

4. The apparatus of claim 1 , wherein the selected address is associated with one of a plurality of banks of a memory array.

5. An apparatus comprising:
a plurality of memory banks;
a plurality of fuse latches, each configured to store a selected address associated with one of the plurality of memory banks;
a plurality of section decoders each configured to generate a section enable signal based on a refresh address;
a plurality of comparators each configured to provide a refresh stop signal at an active level if the selected address matches the refresh address;
a plurality of logic circuits each configured to pass the section enable signal if the refresh stop signal is inactive and each configured to suppress the section enable signal if the refresh stop signal is active; and
a plurality of refresh circuits, each associated with one of the plurality of memory banks, wherein each of the plurality of refresh circuits is configured to generate the refresh address as part of a refresh operation on the associated bank, refresh a word line associated with the refresh address if the refresh stop signal is inactive and not refresh the word line if the refresh stop signal is active, wherein the refresh address is associated with a plurality of word lines, and wherein all of the plurality of word lines are not refreshed if the refresh stop signal is active.

6. The apparatus of claim 5 , wherein each of the selected addresses is associated with a defective word line in the associated one of the plurality of memory banks.

7. The apparatus of claim 5 , wherein the refresh address is associated with a plurality of word lines in the associated one of the plurality of memory banks.

8. The apparatus of claim 7 , wherein if there is match between the selected address and the refresh address none of the plurality of word lines associated with the refresh address are refreshed.

9. The apparatus of claim 7 , wherein the selected address is associated with one of the plurality of word lines, and wherein if there is a match between the selected address and the refresh address, then the one of the plurality of word lines is not refreshed and a remainder of the plurality of word lines are refreshed.

10. The apparatus of claim 7 , wherein the plurality of word lines represent a word line in each of a plurality of sections of the associated one of the plurality of memory banks.

11. A method comprising:
generating, by a refresh address generator, a refresh address as part of a refresh operation on a bank of a memory array, wherein the refresh address is associated with a plurality of word lines;
generating, by a section decoder, a section enable signal based on the refresh address;
comparing, by a comparator, the refresh address to a selected address stored in a fuse latch and providing a refresh stop signal at an active level if there is a match;
passing, by a logic circuit, the section enable signal if the refresh stop signal is inactive and suppressing, by the logic circuit, the section enable signal if the refresh stop signal is active; and
refreshing, by a row decoder, a word line of the memory array associated with the refresh address if the refresh stop signal is at an inactive level, and not refreshing the word line if the refresh stop signal is at the active level, wherein all of the plurality of word lines are not refreshed if the refresh stop signal is active.

12. The method of claim 11 , further comprising refreshing a plurality of word lines associated with the refresh address.

13. The method of claim 12 , further comprising refreshing the plurality of word lines in each of a plurality of sections of the bank.

14. The method of claim 12 , further comprising not refreshing any of the plurality of word lines when the refresh stop signal is at the active level.

15. The method of claim 14 , further comprising repairing the plurality of word lines.

16. The method of claim 12 , wherein one of the plurality of word lines is associated with the selected address, and wherein the method further comprising not refreshing the one of the plurality of word lines and refreshing a remainder of the plurality of word lines when the refresh stop signal is at the active level.

17. The method of claim 11 , further comprising identifying the selected address by determining that a word line associated with the selected address is defective.

Assignees

• Micron Technology Inc

Inventors

• Fujiwara Yoshinori
• Gadamsetty Harish V
• Howe Gary
• Montierth Dennis G
• Shore Michael A
• Johnson Jason M

Classifications

• G11C2029/1202

  Word line control · CPC title

• G11C2029/1806

  Address conversion or mapping, i.e. logical to physical address · CPC title

• G11C11/40622 Primary

  Partial refresh of memory arrays · CPC title

• G11C29/787

  using a fuse hierarchy · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title