Methods for on-die memory termination and memory devices and systems employing the same

Patent metadata

Field	Value
Publication number	US-10950282-B2
Application number	US-201916540011-A
Country	US
Kind code	B2
Filing date	Aug 13, 2019
Priority date	Nov 22, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

First claim

What is claimed is:

1. A method of operating a memory system, comprising:
receiving a first command instructing a memory device of the memory system to enter an on-die termination mode;
in response to the first command, placing the memory device in the on-die termination mode; and
maintaining the memory device in the on-die termination mode for longer than a duration of a data communication of the memory system.

2. The method of claim 1 , wherein the first command includes a number of bursts or clock cycles for which the memory device is to remain in the on-die termination mode.

3. The method of claim 1 , wherein maintaining the memory device in the on-die termination mode for longer than a duration of the data communication of the memory system comprises maintaining the memory device in the on-die termination mode until receiving a second command instructing the memory device to exit the on-die termination mode.

4. The method of claim 1 , further comprising:
receiving a second command instructing the memory device to exit the on-die termination mode; and
in response to the second command, exiting the memory device from the on-die termination mode.

5. The method of claim 1 , wherein the data communication is a first data communication, the method further comprising:
receiving a second command subsequent to the first command, the second command instructing the memory device to perform a second data communication; and
in response to the second command:
exiting the memory device from the on-die termination mode;
performing, with the memory device, the second data communication; and
reverting the memory device to the on-die termination mode after performing the second data communication.

6. The method of claim 5 , wherein the second data communication is one of a read or a write operation.

7. The method of claim 1 , wherein the memory device is a dynamic random access memory (DRAM) device.

8. A method of operating a memory device, the method comprising:
receiving a first command at the memory device instructing a portion of the memory device to enter an on-die termination mode;
receiving a second command instructing the portion to exit the on-die termination mode; and
maintaining, at the portion, the on-die termination mode based at least in part on the first command until receiving the second command.

9. The method of claim 8 , wherein the portion corresponds to a channel of the memory device.

10. The method of claim 8 , wherein the second command further instructs the portion to perform a communication, and wherein the portion is configured, in response to the command, to:
perform the communication, and
reverting to the on-die termination mode after performing the communication.

11. A memory device, comprising:
circuitry configured to implement an on-die termination mode at a portion of the memory device;
wherein the circuitry is configured, in response to a single command to the portion, to implement the on-die termination mode at the portion during more than one data communication of the memory device.

12. The memory device of claim 11 , wherein the circuitry is configured to implement the on-die termination mode at the portion in response to a first command to implement the on-die termination mode, and to remain in the on-die termination mode until receiving a second command to exit the on-die termination mode.

13. The memory device of claim 11 , wherein the circuitry is configured to implement the on-die termination mode at the portion until a threshold number of data communications are performed by the memory device, wherein the threshold number is indicated in the single command to the portion.

14. The memory device of claim 11 , wherein the circuitry is configured to implement the on-die termination mode at the portion in response to a command instructing the portion to perform a data communication, wherein the memory portion is configured to automatically revert to the on-die termination mode following the data communication.

15. The memory device of claim 11 , wherein the memory device is dynamic random access memory (DRAM) device.

16. The memory device of claim 11 , wherein portion corresponds to a channel of the memory device.

Assignees

• Micron Technology Inc

Inventors

• Howe Gary
• Stave Eric J
• Kinsley Thomas H
• Prather Matthew A

Classifications

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C2207/10

  Aspects relating to interfaces of memory device to external buses · CPC title