Apparatuses and methods for timing domain crossing

Patent metadata

Field	Value
Publication number	US-10318238-B2
Application number	US-201816107867-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	May 12, 2014
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

First claim

What is claimed is:

1. An apparatus, comprising:
an input circuit configured to latch a first signal to provide a second signal;
an output circuit configured to receive the second signal and provide a third signal responsive to the received second signal and a clock signal; and
a pulse generator circuit configured to delay the third signal and provide a feedback pulse,
wherein the input circuit is configured to be reset by an edge of the feedback pulse responsive to the delayed third signal.

2. The apparatus of claim 1 , wherein the input circuit is configured to reset latching the first signal responsive to the feedback pulse.

3. The apparatus of claim 1 , wherein the pulse generator circuit is configured to produce one of rising and trailing edges of the feedback pulse responsive to one of rising and trailing edges of the third signal.

4. The apparatus of claim 3 , wherein the pulse generator circuit is configured to produce the other of rising and trailing edges of the feedback pulse responsive to a delayed one of rising and trailing edges of the third signal.

5. The apparatus of claim 1 , wherein the first signal latched by the input circuit is received from a first timing domain.

6. The apparatus of claim 1 , wherein the third signal provided by the output circuit is transferred to a second timing domain.

7. The apparatus of claim 1 , wherein the first signal latched by input circuit is received from a first timing domain, and
wherein the third signal provided by the output circuit is transferred to a second timing domain.

8. The apparatus of claim 1 , wherein the pulse generator circuit is configured to provide the feedback pulse regardless of the third signal when the pulse generator circuit receives a power-up-reset signal.

9. The apparatus of claim 1 , wherein the output circuit is configured to provide the third signal in synchronism with the clock signal.

10. The apparatus of claim 1 , wherein the first signal is provided asynchronously to the clock signal.

11. An apparatus, comprising:
a latch circuit;
an output circuit configured to receive an input signal provided by the latch circuit based on an event signal latched by the latch circuit, the output circuit further configured to provide an output signal responsive to the input signal and a clock signal; and
a pulse generator circuit configured to receive the output signal and provide a feedback pulse to the latch circuit,
wherein the latch circuit is configured to be reset by an edge of the feedback pulse responsive to the output signal delayed by the pulse generator circuit.

12. The apparatus of claim 11 , wherein the latch circuit is configured to reset latching the input signal responsive to the feedback pulse.

13. The apparatus of claim 11 , wherein the input signal is received from a first timing domain.

14. The apparatus of claim 11 , wherein the output signal is transferred to a second timing domain.

15. The apparatus of claim 11 , wherein the pulse generator circuit is configured to provide the feedback pulse regardless of the output signal when the pulse generator circuit receives a power-up-reset signal.

16. The apparatus of claim 11 , wherein the input signal corresponds to an input event and the output signal corresponds to an output event.

17. An apparatus, comprising:
a timing domain transfer circuit configured to:
receive an event signal from a first timing domain, and
provide the event signal as an output signal to a second timing domain,

wherein the timing domain transfer circuit further includes a pulse generator circuit configured to provide feedback based, at least in part, on the output signal delayed, and
wherein the feedback is used to mark the event signal as transferred.

18. The apparatus of claim 17 , wherein the feedback comprises only one feedback signal.

19. The apparatus of claim 18 , wherein the one feedback signal is based, at least in part, on the event signal output by the timing domain transfer circuit.

20. The apparatus of claim 17 , wherein the timing domain transfer circuit is further configured to mark the event signal as transferred based, at least in part, on the output signal of the timing domain transfer circuit.

Assignees

• Micron Technology Inc

Inventors

• Huber Brian
• Howe Gary

Classifications

• G06F5/06 Primary

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title