Apparatuses and methods for bad row mode

Patent metadata

Field	Value
Publication number	US-11915775-B2
Application number	US-202117449297-A
Country	US
Kind code	B2
Filing date	Sep 29, 2021
Priority date	Sep 29, 2021
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.

First claim

What is claimed is:

1. A method comprising:
entering a memory into a bad row mode to disable a selected row of the memory and test a repair logic configured to detect defective rows of the memory;
disabling the selected row of the memory, wherein disabling the selected row includes causing the selected row to temporarily appear to be a defective row by causing failure of an access operation on the selected row, and wherein the access operation is caused to fail by changing a value of at least one data bit in the selected row;
detecting, using the repair logic configured to detect the defective rows of the memory, the selected row as the defective row responsive to the failure of the access operation on the selected row;
performing a post-package repair (PPR) operation on the selected row;
testing an address associated with the selected row; and
exiting the memory from the bad row mode, wherein the selected row is disabled only while the memory is in the bad row mode.

2. The method of claim 1 , wherein disabling the selected row includes blocking an activate command, a column command, changing data read from the selected row or combinations thereof.

3. The method of claim 1 , further comprising determining if the selected row has been previously repaired and not disabling the address associated with the selected row if the selected row has been previously repaired.

4. The method of claim 1 , further comprising storing an address associated with the selected row in a fuse array of the memory.

5. The method of claim 1 , further comprising storing an address associated with the selected row in a soft PPR (sPPR) latch of the memory.

6. The method of claim 1 , wherein the PPR operation includes changing a state of one or more fuses to remap an address associated with the selected row to a redundant row of the memory.

7. The method of claim 1 , further comprising:
writing test data to the memory;
reading read data from the memory;
comparing the read data to the test data to identify the selected row; and
performing the PPR operation on the identified selected row.

8. An apparatus comprising:
a memory array comprising a plurality of word lines, each associated with one of a plurality of row addresses;
a repair circuit configured to remap a plurality of repaired addresses to a respective one of a plurality of redundant word lines, and
a disable control circuit configured to receive a row address, compare the received row address to a selected row address, and provide a kill signal at an active level,
wherein responsive to the kill signal at the active level, access operations to a selected word line of the plurality of word lines associated with the selected address are caused to fail to cause the selected row to temporarily appear to be a defective row by changing a value of at least one data bit in the selected word line,
wherein, when the apparatus is entered into a bad row mode to disable the selected word line and test a repair logic configured to detect defective rows of the memory array, the selected word line is detected as the defective row responsive to a failure of an access operation on the selected row, the disable control circuit disables the selected word line, and the repair circuit performs a post-package repair (PPR) operation on the selected word line, and
wherein, when the apparatus is exited from the bad row mode, the selected word line is not disabled.

9. The apparatus of claim 8 , wherein if the selected row address matches one of the plurality of repaired addresses, the kill signal is not provided at an active level.

10. The apparatus of claim 8 , wherein the disable control circuit stores the selected address in a soft PPR latch.

11. The apparatus of claim 8 , wherein the selected row address is stored in a fuse array and a redundant row decoder.

12. The apparatus of claim 8 , wherein the kill signal is provided at the active level only when the received row address matches the selected row address and a bad row mode enable signal is active.

13. A system comprising:
a memory comprising:
a repair circuit configured to remap a plurality of repaired addresses to a respective one of a plurality of redundant word lines;
a disable control circuit configured to prevent read operations to a word line associated with a selected address when the memory is in a bad row mode to disable the word line and test a repair logic configured to detect defective rows of the memory, wherein the disable control circuit is configured to cause failure of an access operation on the word line associated with the selected address to cause the word line to temporarily appear to be a defective row by changing a value of at least one data bit in the selected word line; and
a controller comprising:
a repair test circuit configured to enter the memory into the bad row mode, and
a bad row identification circuit configured to test the memory to identify the word line as the defective row based on the failure of the access operation and perform a post package repair (PPR) operation on the selected address,

wherein after the PPR operation the selected address is one of the plurality of repaired addresses,
wherein the word line associated with the selected address is disabled when the memory is in the bad row mode, and
wherein the word line associated with the selected address is not disabled when the memory is exited from the bad row mode.

14. The system of claim 13 , wherein the disable control circuit is configured to not prevent read operations to the word line associated with the selected address if the selected address is one of the plurality of repaired addresses.

15. The system of claim 13 , wherein the repair test circuit is configured to provide the selected address.

16. The system of claim 13 , wherein the repair test circuit is configured to enter the memory into the bad row mode by providing a multi-purpose command, writing a value to a mode register of the memory, changing a fuse setting of the memory, or combinations thereof.

17. The system of claim 13 , wherein the memory is configured to store the selected address in a soft PPR latch.

18. The system of claim 13 , wherein the memory is configured to store the selected address in a fuse array.

19. The method of claim 1 , wherein changing the value of the at least one data bit in the selected row comprises inverting values of data bits in the selected row.

20. The method of claim 1 , wherein changing the value of the at least one data bit in the selected row comprises randomizing multiple bits in the selected row.

21. The method of claim 1 , wherein changing the value of the at least one data bit in the selected row comprises replacing multiple bits in the selected row with a set pattern.

Assignees

• Micron Technology Inc

Inventors

• Riley Jack
• Smith Scott
• Mohr Christian
• Howe Gary
• Alzheimer Joshua
• Fujiwara Yoshinori
• Ayyapureddi Sujeet
• Rooney Randall

Classifications

• G11C29/4401 Primary

  for self repair · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/46

  Test trigger logic · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/787 Primary

  using a fuse hierarchy · CPC title