Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Patent metadata

Field	Value
Publication number	US-12426316-B2
Application number	US-202217993438-A
Country	US
Kind code	B2
Filing date	Nov 23, 2022
Priority date	Jan 4, 2019
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon;
exposing a portion of the fin;
etching the portion of the fin to form a trench separating a first fin portion and a second fin portion;
forming a layer comprising silicon in the trench;
forming an oxidation catalyst layer on the layer comprising silicon; and
oxidizing the layer comprising silicon in the presence of the oxidation catalyst layer.

2. The method of claim 1 , further comprising:
recessing the layer comprising silicon in the trench prior to forming the oxidation catalyst layer.

3. The method of claim 1 , wherein oxidizing the layer comprising silicon in the presence of the oxidation catalyst layer comprises using a wet oxidation process.

4. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon, the fin having a top and sidewalls, wherein the fin has a trench separating a first fin portion and a second fin portion;
forming a first gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of the first fin portion;
forming a second gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of the second fin portion; and
forming an isolation structure in the trench of the fin, the isolation structure between the first gate structure and the second gate structure, wherein the isolation structure comprises a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

5. The method of claim 4 , wherein the oxidation catalyst layer comprises aluminum oxide.

6. The method of claim 4 , wherein the oxidation catalyst layer comprises lanthanum oxide.

7. The method of claim 4 , wherein the isolation structure further comprises a third dielectric material laterally surrounded by an upper portion of the first dielectric material, the third dielectric material on an upper surface of the oxidation catalyst layer.

8. The method of claim 7 , wherein the third dielectric material is further on an upper surface of the second dielectric material.

9. The method of claim 4 , wherein the oxidation catalyst layer has an upper surface co-planar with an upper surface of the second dielectric material.

10. The method of claim 4 , wherein the oxidation catalyst layer has an upper surface above an upper surface of the second dielectric material.

11. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction;
forming a first isolation structure over a first end of the fin;
forming a gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of a region of the fin, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
forming a second isolation structure over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction, wherein the first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

12. The method of claim 11 , wherein the first isolation structure and the second isolation structure both further comprise a third dielectric material laterally surrounded by an upper portion of the first dielectric material, the third dielectric material on an upper surface of the oxidation catalyst layer.

13. The method of claim 12 , wherein the third dielectric material is further on an upper surface of the second dielectric material.

14. The method of claim 11 , wherein the oxidation catalyst layer has an upper surface co-planar with an upper surface of the second dielectric material.

15. The method of claim 11 , wherein the oxidation catalyst layer has an upper surface above an upper surface of the second dielectric material.

16. The method of claim 11 , wherein the first and second isolation structures induce a compressive stress on the fin.

17. The method of claim 16 , wherein the gate electrode is a P-type gate electrode.

18. The method of claim 11 , wherein the first isolation structure has a width along the direction, the gate structure has the width along the direction, and the second isolation structure has the width along the direction.

19. The method of claim 18 , wherein a center of the gate structure is spaced apart from a center of the first isolation structure by a pitch along the direction, and a center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the direction.

20. The method of claim 11 , wherein the first and second isolation structures are both in a corresponding trench in an inter-layer dielectric layer.

21. The method of claim 11 , further comprising:
forming a first source or drain region between the gate structure and the first isolation structure; and
forming a second source or drain region between the gate structure and the second isolation structure.

22. The method of claim 21 , wherein the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium.

23. The method of claim 11 , wherein the gate structure further comprises a high-k dielectric layer between the gate electrode and the fin and along sidewalls of the gate electrode.

24. The method of claim 11 , wherein the oxidation catalyst layer comprises aluminum oxide or lanthanum oxide.

Assignees

• Intel Corp

Inventors

• Guler Leonard
• Lindert Nick
• Guha Biswajeet
• Sivakumar Swaminathan
• Ghani Tahir

Classifications

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10W10/0142

  the dielectric materials being chemical transformed from non-dielectric materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title