SRAM with channel count contrast for greater read stability

Patent metadata

Field	Value
Publication number	US-12484207-B2
Application number	US-202117560913-A
Country	US
Kind code	B2
Filing date	Dec 23, 2021
Priority date	Dec 23, 2021
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

First claim

What is claimed is:

1 . A static random-access memory (SRAM) bit-cell structure, comprising:
a pass-gate transistor structure of n-type conductivity, comprising a first gate electrode around a stack of a first number of active channel regions comprising a crystalline material, and an inactive channel region also comprising the crystalline material; a pull-down transistor structure of n-type conductivity, the pull-down transistor structure comprising a second gate electrode around a stack of a second number of active channel regions, greater than the first number of channel regions; and a pull-up transistor, wherein the pull-up transistor further comprises a third gate electrode around a stack of a third number of active channel regions, and wherein the third number of active channel regions is different than the first number of active channel regions.

2 . The SRAM bit-cell structure of claim 1 , wherein the inactive channel region has a first concentration of an impurity exceeding a second concentration of the impurity in the first number of channel regions.

3 . The SRAM bit-cell structure of claim 2 , wherein the first concentration of the impurity is at least 1e19 cm-3 within the inactive channel region.

4 . The SRAM bit-cell structure of claim 2 , wherein:
the pass-gate transistor structure comprises a first source region coupled to a first drain region through the first number of channel regions; the pull-down transistor structure comprises a second source region coupled to a second drain region through the second number of channel regions; the first and second source regions and the first and second drain regions have N-type conductivity; and the inactive channel region has P-type conductivity.

5 . The SRAM bit-cell structure of claim 2 , wherein the impurity is boron or gallium.

6 . The SRAM bit-cell structure of claim 1 , wherein the inactive channel region is over the first number of active channel regions, between a front-side metallization level and the first number of active channel regions.

7 . The SRAM bit-cell structure of claim 1 , wherein the inactive channel region is under the first number of active channel regions, the first number of active channel regions between a front-side metallization level and the inactive channel region.

8 . The SRAM bit-cell structure of claim 1 , wherein:
the first number of active channel regions comprise a crystalline material and the second number of active channel regions comprise the crystalline material; and individual ones of the second number of active channel regions are colinear with individual ones of the first number of active channel regions.

9 . The SRAM bit-cell structure of claim 8 , wherein at least one of second number of active channel regions is coplanar with the inactive channel region, which is over or under the first number of active channel regions.

10 . The SRAM bit-cell structure of claim 9 , wherein the inactive channel region is over the first number of active channel regions, between a front-side metallization level and the first number of active channel regions.

11 . The SRAM bit-cell structure of claim 9 , wherein the inactive channel region is under the first number of active channel regions, the first number of active channel regions between a front-side metallization level and the inactive channel region.

12 . The SRAM bit-cell structure of claim 8 , wherein:
the first gate electrode and the second gate electrode have substantially the same composition; and a first gate insulator between the first gate electrode and the first number of channel regions has substantially the same composition as a second gate insulator between the second gate electrode and the second number of channel regions.

13 . A device comprising:
a microprocessor comprising:
an arithmetic logic unit; and
a cache memory comprising an SRAM array, wherein the SRAM array comprises a plurality of bit-cells and each bit cell comprises the SRAM structure of claim 1 ; and
a power supply coupled to power the microprocessor.

14 . The device of claim 13 , further comprising a battery coupled to the power supply.

15 . A method of fabricating a static random-access memory (SRAM) structure, the method comprising:
receiving a transistor material stack including a plurality of bilayers comprising sacrificial material and channel material; electrically inactivating at least one first layer of the channel material within a pass-gate transistor region by introducing a first concentration of an impurity exceeding a second concentration of the impurity in remaining layers of the channel material without introducing the first concentration of the impurity in the first layer of the channel material within a pull-down transistor region; patterning the transistor material stack into one or more fins including a first number of active channel regions within the pass-gate transistor region and a second number of active channel regions, greater than the first number, within the pull-down transistor region; and forming a gate stack around the first number of active channel regions, and around the second number of active channel regions.

16 . The method of claim 15 , wherein introducing the first concentration of the impurity into the first layer of the channel material comprises:
implanting the impurity within the first layer of the channel material from either a front side or back side of the transistor material stack.

17 . The method of claim 16 , wherein the SRAM structure comprises n-type pass-gate and pull-down transistors, and the impurity is a p-type impurity.

Assignees

• Intel Corp

Inventors

• Ong Clifford
• Guler Leonard
• Hasan Mohammad
• Ghani Tahir

Classifications

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title