Cavity spacer for nanowire transistors

Patent metadata

Field	Value
Publication number	US-11929396-B2
Application number	US-202217725471-A
Country	US
Kind code	B2
Filing date	Apr 20, 2022
Priority date	Jun 29, 2018
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a base;
a body over the base, the body comprising a semiconductor material, the body being in the form of a nanowire, nanoribbon or nanosheet and having a first end portion and a second end portion;
a gate structure wrapped around the body between the first end portion and the second end portion, the gate structure comprising a gate electrode and a gate dielectric between the gate electrode and the body;
a source region laterally adjacent to and in contact with the first end portion;
a drain region laterally adjacent to and in contact with the second end portion;
a first spacer material on opposite sides of the gate structure, the first spacer material above the first end portion of the body;
a second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body, the second spacer material having a composition; and
a dielectric material layer beneath the source region and beneath the drain region and in contact with a bottommost surface of the source region and the drain region, the dielectric material layer having a composition the same as the composition of the second spacer material, and the dielectric material discontinuous with the second spacer material.

2. The integrated circuit structure of claim 1 , wherein the body is a first body of two or more bodies extending horizontally between the source region and the drain region.

3. The integrated circuit structure of claim 2 , wherein the two or more bodies are arranged in a spaced-apart vertical stack.

4. The integrated circuit structure of claim 1 , wherein the body is a nanowire.

5. The integrated circuit structure of claim 1 , wherein the body is a nanoribbon.

6. An integrated circuit structure, comprising:
a base;
a body over the base, the body comprising a semiconductor material, the body being in the form of a nanowire, nanoribbon or nanosheet and having a first end portion and a second end portion;
a gate structure wrapped around the body between the first end portion and the second end portion, the gate structure comprising a gate electrode and a gate dielectric between the gate electrode and the body;
a source region laterally adjacent to and in contact with the first end portion;
a drain region laterally adjacent to and in contact with the second end portion;
a first spacer material on opposite sides of the gate structure, the first spacer material above the first end portion of the body;
a second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body, the second spacer material further beneath the source region and beneath the drain region and in contact with a bottommost surface of the source region and the drain region, wherein a portion of the second spacer material beneath the source region is discontinuous with a portion of the second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body, and wherein a portion of the second spacer material beneath the drain region is discontinuous with a portion of the second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body.

7. The integrated circuit structure of claim 6 , wherein the body is a first body of two or more bodies extending horizontally between the source region and the drain region.

8. The integrated circuit structure of claim 7 , wherein the two or more bodies are arranged in a spaced-apart vertical stack.

9. The integrated circuit structure of claim 6 , wherein the body is a nanowire.

10. The integrated circuit structure of claim 6 , wherein the body is a nanoribbon.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a base;
a body over the base, the body comprising a semiconductor material, the body being in the form of a nanowire, nanoribbon or nanosheet and having a first end portion and a second end portion;
a gate structure wrapped around the body between the first end portion and the second end portion, the gate structure comprising a gate electrode and a gate dielectric between the gate electrode and the body;
a source region laterally adjacent to and in contact with the first end portion;
a drain region laterally adjacent to and in contact with the second end portion;
a first spacer material on opposite sides of the gate structure, the first spacer material above the first end portion of the body;
a second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body, the second spacer material having a composition; and
a dielectric material layer beneath the source region and beneath the drain region and in contact with a bottommost surface of the source region and the drain region, the dielectric material layer having a composition the same as the composition of the second spacer material and the dielectric material discontinuous with the second spacer material.

12. The computing device of claim 11 , further comprising:
a memory coupled to the board.

13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a base;
a body over the base, the body comprising a semiconductor material, the body being in the form of a nanowire, nanoribbon or nanosheet and having a first end portion and a second end portion;
a gate structure wrapped around the body between the first end portion and the second end portion, the gate structure comprising a gate electrode and a gate dielectric between the gate electrode and the body;
a source region laterally adjacent to and in contact with the first end portion;
a drain region laterally adjacent to and in contact with the second end portion;
a first spacer material on opposite sides of the gate structure, the first spacer material above the first end portion of the body;
a second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body, the second spacer material having a composition, the second spacer material further beneath the source region and beneath the drain region and in contact with a bottommost surface of the source region and the drain region, wherein a portion of the second spacer material beneath the source region is discontinuous with a portion of the second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body, and wherein a portion of the second spacer material beneath the drain region is discontinuous with a portion of the second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body.

17. The computing device of claim 16 , further comprising:
a memory coupled to the board.

18. The computing device of claim 16 , further comprising:
a communication chip coup

Assignees

• Intel Corp

Inventors

• Hsu William
• Guha Biswajeet
• Guler Leonard
• Chakrabarty Souvik
• Kang Jun Sung
• Beattie Bruce
• Ghani Tahir

Classifications

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title