Non-planar transistors with channel regions having varying widths

Patent metadata

Field	Value
Publication number	US-11569231-B2
Application number	US-201916354669-A
Country	US
Kind code	B2
Filing date	Mar 15, 2019
Priority date	Mar 15, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a body comprising semiconductor material and having a length, the body further having a first width at a first portion of the length and a second width at a second portion of the length and a third width at a third portion of the length, the first and second and third widths perpendicular to the length, the first different from the second width, and the third width different from the second width and different from the first width;
a first gate structure at least on top and sidewalls of the first portion of the body; and
a second gate structure at least on top and sidewalls of the second portion of the body.

2. The device of claim 1 , wherein the first width is less than 10 nm, and the second width is more than 12 nm.

3. The device of claim 1 , wherein the body is a first body, the device further comprising:
a second body comprising semiconductor material and having a length, the second body further having a fourth width at a first portion of its length and a fifth width at a second portion of its length, the fourth and fifth widths perpendicular to the length of the second body and being 2 nm or more different from one another;
a third gate structure at least on top and sidewalls of the first portion of the second body; and
a fourth gate structure at least on top and sidewalls of the second portion of the second body.

4. The device of claim 3 , wherein each of the first body and the second body has a first side and an opposing second side, the first side of the first body facing the first side of the second body, the first sides of the first and second bodies having a distance between them that varies less than 1 nm along their respective lengths.

5. The device of claim 3 , wherein each of the first body and the second body has a first side and an opposing second side, the first side of the first body facing the first side of the second body, the first sides having a distance between them that varies more than 1 nm along their respective lengths, due to changes in width of the respective bodies.

6. The device of claim 3 , wherein one or more of the first, second, third, and fourth gate structures wraps around its respective body portion to provide a gate-all-around configuration.

7. The device of claim 3 , wherein one or more of the first, second, third, and fourth gate structures is on top and sides of its respective body portion to provide a tri-gate configuration.

8. The device of claim 3 , wherein the semiconductor material of the first body is compositionally distinct from the semiconductor material of the second body.

9. The device of claim 1 , wherein a line width roughness (LWR) of the first portion of the length of the body is at most 7 Angstrom.

10. The device of claim 1 , wherein a transition from the first width to the second width in the body occurs with a transition angle of 85 to 90 degrees.

11. The device of claim 1 , wherein a transition from the first width to the second width in the body occurs within less than 1 nm along a length of the body.

12. The device of claim 1 , wherein the body has a first side and an opposing second side, and a transition from the first width to the second width is accomplished in a symmetrical fashion, in that both the first and second sides of the body change relative to an imaginary central axis passing along the length of the body.

13. The device of claim 1 , wherein the body has a first side and an opposing second side, and a transition from the first width to the second width is accomplished in an asymmetrical fashion, in that one the first side or the second side of the body varies to provide the change in width and the other of the first and second side of the body remains relatively constant.

14. The device of claim 1 , wherein the first width is different from the second width by at least 8 nm.

15. A computing system comprising the device of claim 1 .

16. An integrated circuit comprising:
a first body and a second body comprising semiconductor material, wherein the first body and the second body are aligned, such that a first imaginary line passing through a center of the first body along a length of the first body substantially passes through a center of the second body along a length of the second body;
a third body and a fourth body comprising semiconductor material, wherein the third body and the fourth body are aligned, such that a second imaginary line passing through a center of the third body along a length of the third body substantially passes through a center of the fourth body along a length of the fourth body, wherein one of the first body, the second body, the third body or the fourth body has a first width, a second width and a third width, the first width different from the second width, and the third width different from the second width and different from the first width;
a first gate structure over the first body and the third body; and
a second gate structure over the second body and the fourth body;
wherein a lateral distance between a sidewall of the first body and a sidewall of the third body is substantially different from a lateral distance between a sidewall of the second body and a sidewall of the fourth body, the sidewall of the first body facing the sidewall of the third body, and the sidewall of the second body facing the sidewall of the fourth body.

17. The integrated circuit of claim 16 , further comprising:
a first source or drain region between the first body and the second body; and a second source or drain region between the third body and the fourth body.

18. The integrated circuit of claim 16 , wherein:
a first width of the first body differs by at least 6 nanometers from at least one of:
a second width of the second body, a third width of the third body, or a fourth width of the fourth body; the first width and the second width are along a direction perpendicular to the first imaginary line passing through the center of the first body; and
the third width and the fourth width are along a direction perpendicular to the second imaginary line passing through the center of the third body.

19. An integrated circuit comprising:
a first body and a second body comprising semiconductor material, the first body having a first sidewall, and the second body having a second sidewall that is colinear with the first sidewall;
a third body and a fourth body comprising semiconductor material, the third body having a third sidewall, and the fourth body having a fourth sidewall that is colinear with the third sidewall, wherein one of the first body, the second body, the third body or the fourth body has a first width, a second width and a third width, the first width different from the second width, and the third width different from the second width and different from the first width; and
a first gate structure over the first body and the third body; and
a second gate structure over the second body and the fourth body;
wherein a lateral distance between the first sidewall of the first body and third sidewall of the third body is substantially a same as a lateral distance between the second sidewall of the second body and the fourth sidewall of the fourth body, the first sidewall of the first body facing the third sidewall of the third body, and the second sidewall of the second body facing the fourth sidewall of the fourth body, and wherein a first width of the first body differs by at least 6 nanometers from at least one of:
a second width of the second body, a third width of the thir

Assignees

• Intel Corp

Inventors

• Snyder Stephen D
• Guler Leonard
• Schenker Richard
• Harper Michael K
• Sivakumar Sam
• Alaan Urusa
• Bojarski Stephanie A
• Bhuwalka Achala

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/246

  of Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3462

  Nanowires · CPC title