Dielectric isolation layer between a nanowire transistor and a substrate

Patent metadata

Field	Value
Publication number	US-11901458-B2
Application number	US-202217850799-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Jun 22, 2018
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a nanowire over a substrate, the nanowire comprising a first semiconductor material;
a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire, and the source region and the drain region having a bottommost surface below the uppermost surface of the first dielectric layer; and
first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region.

2. The integrated circuit device of claim 1 , wherein the first dielectric layer is between the substrate and a bottom surface of both the source region and the drain region.

3. The integrated circuit device of claim 1 , wherein first portions of the source region and the drain region are in direct contact with the substrate, and the first dielectric layer is on the substrate between second portions of the source region and the drain region.

4. The integrated circuit device of claim 1 , further comprising a second nanowire over the nanowire.

5. The integrated circuit device of claim 4 , further comprising an additional dielectric layer on and around the second nanowire, the additional dielectric layer comprising the second dielectric material.

6. The integrated circuit device of claim 5 , further comprising a portion of the gate electrode between the additional dielectric layer on the second nanowire and the second dielectric layer on the nanowire.

7. The integrated circuit device of claim 1 , wherein the first dielectric material comprises silicon and at least one of oxygen and nitrogen.

8. The integrated circuit device of claim 1 , wherein the second dielectric material comprises hafnium and oxygen.

9. The integrated circuit device of claim 1 , wherein the first and second gate spacers each includes multiple portions that are discontinuous from one another.

10. The integrated circuit device of claim 1 , wherein the source region and the drain region comprise at least one source region nanowire and at least one drain region nanowire, respectively.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a nanowire over a substrate, the nanowire comprising a first semiconductor material;
a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire, and the source region and the drain region having a bottommost surface below the uppermost surface of the first dielectric layer; and
first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region.

12. The computing device of claim 11 , further comprising:
a memory coupled to the board.

13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16. The computing device of claim 11 , wherein the first dielectric layer is between the substrate and a bottom surface of both the source region and the drain region.

17. The computing device of claim 11 , wherein first portions of the source region and the drain region are in direct contact with the substrate, and the first dielectric layer is on the substrate between second portions of the source region and the drain region.

18. The computing device of claim 11 , further comprising a second nanowire over the nanowire.

19. The computing device of claim 18 , further comprising an additional dielectric layer on and around the second nanowire, the additional dielectric layer comprising the second dielectric material.

20. The computing device of claim 19 , further comprising a portion of the gate electrode between the additional dielectric layer on the second nanowire and the second dielectric layer on the nanowire.

21. An integrated circuit device comprising:
a nanowire over a substrate, the nanowire comprising a first semiconductor material;
a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire, wherein first portions of the source region and the drain region are in direct contact with the substrate, and the first dielectric layer is on the substrate between second portions of the source region and the drain region; and
first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region.

22. An integrated circuit device comprising:
a nanowire over a substrate, the nanowire comprising a first semiconductor material;
a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a

Assignees

• Intel Corp

Inventors

• Beattie Bruce E
• Guler Leonard
• Guha Biswajeet
• Kang Jun Sung
• Hsu William

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/795

  being in lateral device isolation regions, e.g. STI · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title