Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach

Patent metadata

Field	Value
Publication number	US-12002810-B2
Application number	US-201816146800-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of nanowires than the second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires, and the first vertical arrangement of nanowires having a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires, wherein the first vertical arrangement of nanowires is over a first fin, the first fin having an uppermost surface, and the second vertical arrangement of nanowires is over a second fin, the second fin having an uppermost surface below the uppermost surface of the first fin, wherein the bottommost nanowire of the first vertical arrangement of nanowires is vertically spaced apart from the first fin by a first distance, and wherein the bottommost nanowire of the second vertical arrangement of nanowires is vertically spaced apart from the second fin by a second distance, the second distance greater than the first distance;
a first gate stack over the first vertical arrangement of nanowires; and
a second gate stack over the second vertical arrangement of nanowires.

2. The integrated circuit of claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width the same as a horizontal width of the nanowires of the second vertical arrangement of nanowires.

3. The integrated circuit of claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width greater than a horizontal width of the nanowires of the second vertical arrangement of nanowires.

4. The integrated circuit of claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width less than a horizontal width of the nanowires of the second vertical arrangement of nanowires.

5. The integrated circuit of claim 1 , further comprising:
first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires; and
second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires.

6. The integrated circuit structure of claim 5 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.

7. The integrated circuit structure of claim 5 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

8. The integrated circuit structure of claim 5 , wherein the first gate stack has dielectric sidewall spacers, and the first epitaxial source or drain structures are first embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the first gate stack, and wherein the second gate stack has dielectric sidewall spacers, and the second epitaxial source or drain structures are second embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the second gate stack.

9. The integrated circuit of claim 5 , further comprising:
a first pair of conductive contact structures coupled to the first epitaxial source or drain structures; and
a second pair of conductive contact structures coupled to the second epitaxial source or drain structures.

10. The integrated circuit structure of claim 9 , wherein at least one of the first and second pairs of conductive contact structures is an asymmetric pair of conductive contact structures.

11. The integrated circuit structure of claim 1 , wherein the first fin has an upper surface above an upper surface of the second fin.

12. The integrated circuit of claim 1 , further comprising:
a gate endcap isolation structure between and in contact with the first gate stack and the second gate stack.

13. The integrated circuit structure of claim 1 , wherein the first and second gate stacks each comprise a high-k gate dielectric layer and a metal gate electrode.

Assignees

• Intel Corp

Inventors

• Crum Dax M
• Guha Biswajeet
• Guler Leonard
• Ghani Tahir

Classifications

• H10D84/8312

  the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/0193

  the components including FinFETs · CPC title